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| description the 4512 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with serial i/o, four 8-bit timers (each timer has a reload register), and 10-bit a-d converter. the various microcomputers in the 4512 group include variations of the built-in memory size as shown in the table below. features l minimum instruction execution time ................................ 0.75 m s (at 4.0 mhz oscillation frequency, in high-speed mode, v dd = 4.0 v to 5.5 v) l supply voltage ..... 4.0 v to 5.5 v (at 4.2 mhz oscillation frequency) product m34512m2-xxxfp M34512M4-xxxfp rom type mask rom mask rom package 32p6b-a 32p6b-a ram size ( 5 4 bits) 128 words 256 words rom (prom) size ( 5 10 bits) 2048 words 4096 words 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. l timers timer 1 ...................................... 8-bit timer with a reload register timer 2 ...................................... 8-bit timer with a reload register timer 3 ...................................... 8-bit timer with a reload register timer 4 ...................................... 8-bit timer with a reload register l interrupt ........................................................................ 8 sources l serial i/o ....................................................................... 8 bit-wide l a-d converter .................. 10-bit successive comparison method l watchdog timer ................................................................. 16 bits l clock generating circuit (ceramic resonator) l led drive directly enabled (port d) application electrical household appliance, consumer electronic products, of- fice automation equipment, etc. pin configuration (top view) m34512mx-xxxfp 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 p0 2 p0 1 p0 0 a in3 a in2 a in1 a in0 int1 d 3 d 4 d 5 d 6 d 7 p2 0 /s ck p2 1 /s out p2 2 /s in d 2 d 1 d 0 p1 3 p1 2 p1 1 p1 0 p0 3 reset cnv ss x out x in v ss v dd n.f int0 outline 32p6b-a n.f: no function however, connect tov ss as an unused pin.
2 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. block diagram ram rom memory i/o port internal peripheral functions timer timer 1 (8 bits) system clock generating circuit timer 2 (8 bits) 128, 256 words 5 4 bits 2048, 4096 words 5 10 bits 4500 series cpu core register b (4 bits) register a (4 bits) register d (3 bits) register e (8 bits) stack register sk (8 levels) interrupt stack register sdp (1level) alu (4 bits) x in -x out timer 3 (8 bits) timer 4 (8 bits) watchdog timer (16 bits) (10 bits 5 4 ch) a-d converter serial i/o (8 bits 5 1) port p0 4 |[go 1 port p1 4 port p2 3 port d 8 3 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. performance overview function 117 0.75 m s (at 4.0 mhz oscillation frequency, in high-speed mode) 2048 words 5 10 bits 4096 words 5 10 bits 128 words 5 4 bits 256 words 5 4 bits eight independent i/o ports. input is examined by skip decision. 4-bit i/o port; each pin is equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. 4-bit i/o port; each pin is equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. 3-bit input port; ports p2 0 , p2 1 and p2 2 are also used as s ck , s out and s in , respectively. 1-bit input; int0 pin is equipped with a key-on wakeup function. 1-bit input; int1 pin is equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 10-bit wide, this is equipped with an 8-bit comparator function. 8-bit 5 1 8 (two for external, four for timer, one for a-d, and one for serial i/o) 1 level 8 levels cmos silicon gate 32-pin plastic molded lqfp(32p6b-a) C20 c to 85 c 4.0 v to 5.5 v 3.0 ma (at v dd = 5.0 v, 4.0 mhz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 m a (at room temperature, v dd = 5 v, output transistors in the cut-off state) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports timers a-d converter serial i/o interrupt subroutine nesting device structure package operating temperature range supply voltage power dissipation (typical value) rom ram d 0 Cd 7 p0 0 Cp0 3 p1 0 Cp1 3 p2 0 Cp2 2 int0 int1 timer 1 timer 2 timer 3 timer 4 sources nesting active mode ram back-up mode m34512m2 M34512M4 m34512m2 M34512M4 i/o i/o i/o input input input 4 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. pin description name power supply ground no function cnv ss reset input system clock input system clock output i/o port d i/o port p0 i/o port p1 input port p2 analog input interrupt input serial data input serial data output serial i/o clock input/output pin v dd v ss n.f cnv ss reset x in x out d 0 Cd 7 p0 0 Cp0 3 p1 0 Cp1 3 p2 0 Cp2 2 a in0 Ca in3 int0, int1 s in s out s ck input/output i/o input output i/o i/o input input input input output i/o function connected to a plus power supply. connected to a 0 v power supply. this pin has no function, and connect to v ss as an unused pin. connect cnv ss to v ss and apply l (0v) to cnv ss certainly. an n-channel open-drain i/o pin for a system reset. when the watchdog timer causes the system to be reset, the reset pin outputs l level. i/o pins of the system clock generating circuit. x in and x out can be connected to ceramic resonator. a feedback resistor is built-in between them. each pin of port d has an independent 1-bit wide i/o function. each pin has an out- put latch. for input use, set the latch of the specified bit to 1. input is examined by skip decision. the output structure is n-channel open-drain. each of ports p0 and p1 serves as a 4-bit i/o port, and it can be used as inputs when the output latch is set to 1. the output structure is n-channel open-drain. every pin of the ports has a key-on wakeup function and a pull-up function. both functions can be switched by software. 3-bit input port. ports p2 0 , p2 1 and p2 2 are also used as s ck , s out and s in , respec- tively. analog input pins for a-d converter. int0, int1 pins accept external interrupts. they also accept the input signal to re- turn the system from the ram back-up state. s in pin is used to input serial data signals by software. s in pin is also used as port p2 2 . s out pin is used to output serial data signals by software. s out pin is also used as port p2 1 . s ck pin is used to input and output synchronous clock signals for serial data transfer by software. s ck pin is also used as port p2 0 . 5 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. notes 1: pins except above have just single function. 2: the input of p2 0 Cp2 2 can be used even when s ck , s out , s in are selected. note: when the p0 0 Cp0 3 and p1 0 Cp1 3 are connected to v ss , turn off their pull-up transistors (register pu0i=0) and also invalidate the key-on wakeup functions (register k0i=0) by software. when these pins are connected to v ss while the key-on wakeup functions are left valid, the system fails to return from ram back-up state. when these pins are open, turn on their pull-up transistors (register pu0i=1) by software, or set the output latch to 0. be sure to select the key-on wakeup functions and the pull-up func- tions with every two pins. if only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) (note when the output latch is set to 0 and pins are open) l after system is released from reset, port is in a high-impedance state un- til it is set the output latch to 0 by software. accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state. l to set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise). (note when connecting to v ss and v dd ) l connect the unused pins to v ss and v dd using the thickest wire at the shortest distance against noise. pin p2 0 p2 1 p2 2 multifunction s ck s out s in multifunction connections of unused pins connection open (when using an external clock). connect to v ss . connect to v ss , or set the output latch to 0 and open. connect to v ss . connect to v ss . connect to v ss . open or connect to v ss (note) open or connect to v ss (note) pin x out n.f d 0 Cd 7 p2 0 /s ck p2 1 /s out p2 2 /s in int0 int1 a in0 Ca in3 p0 0 Cp0 3 p1 0 Cp1 3 pin s ck s out s in multifunction p2 0 p2 1 p2 2 definition of clock and cycle l system clock the system clock is the basic clock for controlling this product. the system clock is selected by the bit 3 of the clock control reg- ister mr. register mr mr 3 0 1 system clock f(x in ) f(x in )/2 note: f(x in )/2 is selected after system is released from reset. l instruction clock the instruction clock is a signal derived by dividing the system clock by 3. the one instruction clock cycle generates the one machine cycle. l machine cycle the machine cycle is the standard cycle required to execute the instruction. table selection of system clock port function port port d port p0 port p1 port p2 i/o unit 1 4 4 3 control instructions sd, rd szd cld op0a iap0 op1a iap1 iap2 control registers pu0, k0 pu0, k0 j1 output structure n-channel open-drain n-channel open-drain n-channel open-drain input output i/o (8) i/o (4) i/o (4) input (3) remark built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) pin d 0 Cd 7 p0 0 Cp0 3 p1 0 Cp1 3 p2 0 /s ck p2 1 /s out p2 2 /s in 6 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. port block diagrams d t q ai p1 2 , p1 3 k0 3 pu 0 3 key-on wakeup input pull-up transistor register a op1a instruction iap1 instruction d t q ai p1 0 , p1 1 k0 2 pu 0 2 key-on wakeup input pull-up transistor op1a instruction iap1 instruction register a d t q ai p0 2 , p0 3 k0 1 pu 0 1 key-on wakeup input pull-up transistor op0a instruction iap0 instruction register a d t q ai p0 0 , p0 1 k0 0 pu 0 0 key-on wakeup input pull-up transistor op0a instruction iap0 instruction register a synchronous clock input for serial transfer register a iap2 instruction p2 0 /s ck j1 0 synchronous clock output for serial transfer j1 1 1 0 p2 1 /s out register a iap2 instruction serial data output j1 1 0 1 p2 2 /s in register a iap2 instruction serial data input this symbol represents a parasitic diode on the port. applied potential to ports p2 0 ep2 2 must be v dd . applied potential to ports d 0 ed 7 must be 12 v. i represents 0, 1, 2, or 3. external interrupt circuit key-on wakeup input int0, int1 d 0 ed 7 sd instruction s r q decoder skip decision (szd instruction) register y rd instruction a in0 ea in3 q1 decoder analog input cld instruction 7 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. external interrupt circuit structure 0 1 i2 2 0 1 exf1 i2 1 snzi1 int1 0 1 i1 2 wakeup skip 0 1 exf0 i1 1 snzi0 int0 rising falling one-sided edge detection circuit both edges detection circuit external 0 interrupt external 1 interrupt wakeup skip rising falling one-sided edge detection circuit both edges detection circuit this symbol represents a parasitic diode on the port. 8 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4- bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, ex- change, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (fig- ure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e fig. 4 tabp p instruction execution example (cy) (m(dp)) (a) addition alu 9 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; ? branching to an interrupt service routine (referred to as an inter- rupt service routine), ? performing a subroutine call, or ? executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subrou- tines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be care- ful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 lev- els are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an inter- rupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and regis- ter b just before an interrupt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call returning to the bm instruction executio n address with the rt instruction, and the b m instruction becomes the nop instruction. (sp) ? 0 (sk 0 ) ? 0001 16 (pc) ? sub1 main program 0002 16 nop address 0000 16 nop 0001 16 bm sub1 subroutine sub1 : nop rt (pc) ? (sk 0 ) (sp) ? 7 note : sk 0 sk 1 sk 2 sk 3 sk 4 sk 5 sk 6 sk 7 (sp) = 0 (sp) = 1 (sp) = 2 (sp) = 3 (sp) = 4 (sp) = 5 (sp) = 6 (sp) = 7 program counter (pc) executing rt instruction executing bm instruction stack pointer (sp) points ??at reset or returning from ram back-up mode. it points ?? by executing the first bm instruction, and the contents of program counter is stored in sk 0 . when the bm instruction is executed after eight stack registers are used ((sp) = 7), (sp) = 0 and the contents of sk 0 is destroyed. 10 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which speci- fies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, reg- ister x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 data pointer (dp) register z (2) register x (4) register y (4) specifying ram digit specifying ram file specifying ram file group 01 01 1 d 7 set specifying bit position port d output latch register y (4) d 5 d 6 d 4 d 0 p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 program counter pc h specifying page pc l specifying address p 6 11 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. program memoy (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. fig- ure 10 shows the rom map of M34512M4. table 1 rom size and pages product m34512m2 M34512M4 rom size ( 5 10 bits) 2048 words 4096 words pages 16 (0 to 15) 32 (0 to 31) a part of page 1 (addresses 0080 16 to 00ff 16 ) is reserved for in- terrupt addresses (figure 11). when an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. when using an interrupt service routine, write the in- struction generating the branch to that routine at an interrupt address. page 2 (addresses 0100 16 to 017f 16 ) is the special page for sub- routine calls. subroutines written in this page can be called from any page with the 1-word instruction (bm). subroutines extending from page 2 to another page can also be called with the bm in- struction when it starts on page 2. rom pattern (bits 7 to 0) of all addresses can be used as data ar- eas with the tabp p instruction. fig. 10 rom map of M34512M4 fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure 90 8765 4321 external 0 interrupt address external 1 interrupt address 0080 16 0082 16 timer 1 interrupt address 0084 16 timer 2 interrupt address 0086 16 timer 3 interrupt address 0088 16 008a 16 00ff 16 timer 4 interrupt address a-d interrupt address serial i/o interrupt address 008c 16 008e 16 0 876 54321 0000 16 0080 16 017 f 16 subroutine special page 007 f 16 00 ff 16 0100 16 0180 16 page 1 page 2 page 0 page 3 pa g e 31 0 fff 16 interrupt address page 9 12 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram. table 2 shows the ram size. figure 12 shows the ram map. fig. 12 ram map table 2 ram size product m34512m2 M34512M4 ram size 128 words 5 4 bits (512 bits) 256 words 5 4 bits (1024 bits) M34512M4 m34512m2 z=0, x=0 to 15 z=0, x=0 to 7 register y register z register x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 7 ram 256 words 5 4 bits (1024 bits) 23 6 15 256 words 128 words ????? ??? 13 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. ? an interrupt activated condition is satisfied (request flag = 1) ? interrupt enable bit is enabled (1) ? interrupt enable flag is enabled (inte = 1) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every inter- rupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; ? an interrupt occurs, or ? the next instruction is skipped with a skip instruction. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its in- terrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources activated condition level change of int0 pin level change of int1 pin timer 1 underflow timer 2 underflow timer 3 underflow timer 4 underflow completion of a-d conversion completion of serial i/o transfer priority level 1 2 3 4 5 6 7 8 interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt a-d interrupt serial i/o interrupt request flag exf0 exf1 t1f t2f t3f t4f adf siof interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt a-d interrupt serial i/o interrupt table 5 interrupt enable bit function occurrence of interrupt enabled disabled skip instruction invalid valid interrupt enable bit 1 0 interrupt address address 0 in page 1 address 2 in page 1 address 4 in page 1 address 6 in page 1 address 8 in page 1 address a in page 1 address c in page 1 address e in page 1 table 4 interrupt request flag, interrupt enable bit and skip in- struction skip instruction snz0 snz1 snzt1 snzt2 snzt3 snzt4 snzad snzsi enable bit v1 0 v1 1 v1 2 v1 3 v2 0 v2 1 v2 2 v2 3 14 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as fol- lows (figure 14). ? program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). ? interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. ? interrupt request flag only the request flag for the current interrupt source is cleared to 0. ? data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an in- terrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning the main routine. (refer to figure 13) fig. 13 program example of interrupt processing ? program counter (pc) ............................................................... each interrupt address ? stack register (sk) .................................................................................................... ? interrupt enable flag (inte) .................................................................. 0 (interrupt disabled) ? interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 ? data pointer, carry flag, registers a and b, skip flag ........ stored in the interrupt stack register (sdp) automatically the address of main routine to be executed when returning fig. 15 interrupt system diagram fig. 14 internal state when interrupt occurs t1f v1 2 exf1 v1 1 exf0 v1 0 address 2 in page 1 address 4 in page 1 address 0 in page 1 t4f v2 1 t3f v2 0 t2f v1 3 address 8 in page 1 address a in page 1 address 6 in page 1 siof v2 3 adf v2 2 completion of serial i/o transfer timer 1 underflow timer 4 underflow timer 3 underflow timer 2 underflow completion of a-d conversion address e in page 1 address c in page 1 request flag (state retained) enable bit enable flag inte activated condition int0 pin (l ? h or h ? l input) int1 pin (l ? h or h ? l input) ei rti interrupt service routine interrupt occurs interrupt is enabled main routine : interrupt enabled state : interrupt disabled state 15 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (6) interrupt control registers ? interrupt control register v1 interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. ? interrupt control register v2 interrupt enable bits of timer 3, timer 4, a-d and serial i/o are as- signed to register v2. set the contents of this register through register a with the tv2a instruction. the tav2 instruction can be used to transfer the contents of register v2 to register a. table 6 interrupt control registers v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 serial i/o interrupt enable bit a-d interrupt enable bit timer 4 interrupt enable bit timer 3 interrupt enable bit interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit note: r represents read enabled, and w represents write enabled. interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) interrupt disabled (snzsi instruction is valid) interrupt enabled (snzsi instruction is invalid) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) interrupt disabled (snzt4 instruction is valid) interrupt enabled (snzt4 instruction is invalid) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 interrupt control register v2 r/w at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 16 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (7) interrupt sequence interrupts only occur when the respective inte flag, interrupt en- able bits (v1 0 Cv1 3 and v2 0 Cv2 3 ), and interrupt request flag are 1. the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt oc- curs after 3 machine cycles only when the three interrupt condi- tions are satisfied on execution of other than one-cycle instructions (refer to figure 16). fig. 16 interrupt sequence t 1 t 2 t 3 t 1 t 2 t 3 t 1 t 2 t 3 system clock t 1 t 2 t 3 exf0, exf1 t1f, t2f, t3f, t4f, adf,siof int0, int1 t 1 t 2 t 3 2 to 3 machine cycles (notes 2, 3) the program starts from the interrupt address. flag cleared interrupt enabled state when an interrupt request flag is set after its interrupt is enabled (note 1) 1 machine cycle ei instruction execution cycle interrupt enable flag (inte) retaining level of system clock for 4 periods or more is necessary. interrupt disabled state external interrupt timer 1, timer 2, timer 3, timer 4, a-d, and serial i/o interrupts interrupt activated condition is satisfied. 2: the address is stacked to the last cycle. 3: this interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied . notes 1: the 4512 group operates in the middle-speed mode after system is released from reset. f (x in ) (middle-speed mode) f (x in ) (high-speed mode) 17 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 7 external interrupt activated conditions name external 0 interrupt external 1 interrupt input pin int0 int1 activated condition when the next waveform is input to int0 pin ? falling waveform (h ? l) ? rising waveform (l ? h) ? both rising and falling waveforms when the next waveform is input to int1 pin ? falling waveform (h ? l) ? rising waveform (l ? h) ? both rising and falling waveforms valid waveform selection bit i1 1 i1 2 i2 1 i2 2 fig. 17 external interrupt circuit structure external interrupts the 4512 group has two external interrupts (external 0 and exter- nal 1). an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupts can be controlled with the interrupt control registers i1 and i2. 0 1 i2 2 0 1 exf1 i2 1 snzi1 int1 0 1 i1 2 wakeup skip 0 1 exf0 i1 1 snzi0 int0 rising falling one-sided edge detection circuit both edges detection circuit external 0 interrupt external 1 interrupt wakeup skip rising falling one-sided edge detection circuit both edges detection circuit this symbol represents a parasitic diode on the port. 18 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to 1 when a valid waveform is input to int0 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. ? external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to int0 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 0 interrupt is as follows. select the valid waveform with the bits 1 and 2 of register i1. clear the exf0 flag to 0 with the snz0 instruction. a set the nop instruction for the case when a skip is performed with the snz0 instruction. ? set both the external 0 interrupt enable bit (v1 0 ) and the inte flag to 1. the external 0 interrupt is now enabled. now when a valid wave- form is input to the int0 pin, the exf0 flag is set to 1 and the external 0 interrupt occurs. (2) external 1 interrupt request flag (exf1) external 1 interrupt request flag (exf1) is set to 1 when a valid waveform is input to int1 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf1 flag can be examined with the skip instruction (snz1). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf1 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. ? external 1 interrupt activated condition external 1 interrupt activated condition is satisfied when a valid waveform is input to int1 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 1 interrupt is as follows. select the valid waveform with the bits 1 and 2 of register i2. clear the exf1 flag to 0 with the snz1 instruction. a set the nop instruction for the case when a skip is performed with the snz1 instruction. ? set both the external 1 interrupt enable bit (v1 1 ) and the inte flag to 1. the external 1 interrupt is now enabled. now when a valid wave- form is input to the int1 pin, the exf1 flag is set to 1 and the external 1 interrupt occurs. 19 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (3) external interrupt control registers ? interrupt control register i1 register i1 controls the valid waveform for the external 0 inter- rupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. ? interrupt control register i2 register i2 controls the valid waveform for the external 1 inter- rupt. set the contents of this register through register a with the ti2a instruction. the tai2 instruction can be used to transfer the contents of register i2 to register a. table 8 external interrupt control registers i1 3 i1 2 i1 1 i1 0 i2 3 i2 2 i2 1 i2 0 not used interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 control enable bit this bit has no function, but read/write is enabled. falling waveform (l level of int1 pin is recognized with the snzi1 instruction)/l level rising waveform (h level of int1 pin is recognized with the snzi1 instruction)/h level one-sided edge detected both edges detected disabled enabled not used interrupt valid waveform for int1 pin/ return level selection bit (note 3) int1 pin edge detection circuit control bit int1 pin timer 3 control enable bit notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 is changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 instruction. 3: when the contents of i2 2 is changed, the external interrupt request flag exf1 may be set. accordingly, clear exf1 flag with the snz1 instruction. interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. falling waveform (l level of int0 pin is recognized with the snzi0 instruction)/l level rising waveform (h level of int0 pin is recognized with the snzi0 instruction)/h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 interrupt control register i2 r/w at ram back-up : state retained at reset : 0000 2 20 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. timers the 4512 group has the following timers. ? programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set- ting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to 1, new data is loaded from the reload reg- ister, and count continues (auto-reload function). ? fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). an interrupt request flag is set to 1 after every n count of a count pulse. fig. 18 auto-reload function ff 16 n 00 16 n : counter initial value count starts reload reload 1st underflow 2nd underflow n+1 count n+1 count time an interrupt occurs or a skip instruction is executed. timer interrupt request flag the contents of counter 1 0 21 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. count source ? instruction clock ? prescaler output (orclk) ? timer 1 underflow ? prescaler output (orclk) ? 16-bit timer underflow ? timer 2 underflow ? prescaler output (orclk) ? timer 3 underflow ? prescaler output (orclk) ? instruction clock structure frequency divider 8-bit programmable binary down counter (link to int0 input) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to int1 input) 8-bit programmable binary down counter 16-bit fixed dividing frequency circuit prescaler timer 1 timer 2 timer 3 timer 4 16-bit timer use of output signal ? timer 1, 2, 3 and 4 count sources ? timer 2 count source ? timer 1 interrupt ? timer 3 count source ? timer 2 interrupt ? timer 4 count source ? timer 3 interrupt ? timer 4 interrupt ? watchdog timer (the 15th bit is counted twice) ? timer 2 count source (16-bit timer underflow) frequency dividing ratio 4, 16 1 to 256 1 to 256 1 to 256 1 to 256 65536 control register w1 w1 w2 w3 w4 the 4512 group timer consists of the following circuits. ? prescaler : frequency divider ? timer 1 : 8-bit programmable timer ? timer 2 : 8-bit programmable timer ? timer 3 : 8-bit programmable timer ? timer 4 : 8-bit programmable timer (timers 1 to 4 have the interrupt function, respectively) ? 16-bit timer prescaler and timers 1 to 4 can be controlled with the timer control registers w1 to w4. the 16-bit timer is a free counter which is not controlled with the control register. each function is described below. table 9 function related timers 22 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 19 timers structure t4f t3f 10 01 00 w3 1 ,w3 0 0 1 w3 3 (note 3) 0 1 w4 3 (note 3) 11 t1f (t2ab) t2f (tab2) 0 1 w2 3 (note 3) 0 1 (note 3) w1 1 (tr1ab) t1ab t1ab (tab1) (t4ab) (tab4) (tr3ab) t3ab t3ab (tab3) q r s 1 - - - - - - - - - - - 15 16 wdf1 wdf2 wef 10 01 00 w2 1 ,w2 0 11 10 01 00 w4 1 ,w4 0 11 timer 4 interrupt timer 3 interrupt not available wrst instruction timer 2 underflow signal timer 1 (8) timer 1 interrupt reload register r1 (8) register b register a timer 1 underflow signal timer 2 (8) reload register r2 (8) register b register a timer 3 (8) reload register r3 (8) register b register a timer 3 underflow signal timer 4 (8) reload register r4 (8) register b register a instruction clock 16-bit timer (wdt) system reset reset signal timer 2 interrupt data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (auto-reload function) notes 1: timer 1 count start synchronous circuit is set by the valid edge of p3 0 /int0 pin selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1. 2: timer 3 count start synchronous circuit is set by the valid edge of p3 1 /int1 pin selected by bits 1 (i2 1 ) and 2 (i2 2 ) of register i2. 3: count source is stopped by clearing to ?. not available not available not available not available orclk q r s w1 0 1 0 i1 0 0 1 i1 1 int0 1/4 1/16 1 0 w1 2 1 0 w1 3 mr 3 1 0 x in divistion circuit (divided by 2) instruction clock internal clock generating circuit (divided by 3) prescaler 0 1 i1 2 one-sided edge detection circuit both edges detection circuit q r s w3 2 1 0 i2 0 0 1 i2 1 int1 0 1 i2 2 one-sided edge detection circuit both edges detection circuit (note 1) (note 2) falling rising falling rising 23 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 10 timer control registers 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating this bit has no function, but read/write is enabled. count source timer 1 underflow signal prescaler output not available 16 bit timer (wdt) underflow signal timer 2 control bit not used timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 w2 3 w2 2 w2 1 w2 0 w3 3 w3 2 w3 1 w3 0 w4 3 w4 2 w4 1 w4 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 w3 1 0 0 1 1 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected count source timer 2 underflow signal prescaler output not available not available timer 3 control bit timer 3 count start synchronous circuit control bit timer 3 count source selection bits 0 1 0 1 w3 0 0 1 0 1 timer control register w3 r/w at ram back-up : state retained at reset : 0000 2 w4 1 0 0 1 1 stop (state retained) operating this bit has no function, but read/write is enabled. count source timer 3 underflow signal prescaler output not available not available timer 4 control bit not used timer 4 count source selection bits 0 1 0 1 w4 0 0 1 0 1 timer control register w4 r/w at ram back-up : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled. 24 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (1) timer control registers ? timer control register w1 register w1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. ? timer control register w2 register w2 controls the count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to trans- fer the contents of register w2 to register a. ? timer control register w3 register w3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. set the contents of this register through register a with the tw3a in- struction. the taw3 instruction can be used to transfer the contents of register w3 to register a. ? timer control register w4 register w4 controls the count operation and count source of timer 4. set the contents of this register through register a with the tw4a instruction. the taw4 instruction can be used to trans- fer the contents of register w4 to register a. (2) precautions note the following for the use of timers. ? prescaler stop the prescaler operation to change its frequency dividing ra- tio. ? count source stop timer 1, 2, 3, or 4 counting to change its count source. ? reading the count value stop timer 1, 2, 3, or 4 counting and then execute the tab1, tab2, tab3, or tab4 instruction to read its data. ? writing to reload registers r1 and r3 when writing data to reload registers r1 or r3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. (3) prescaler prescaler is a frequency divider. its frequency dividing ratio can be selected. the count source of prescaler is the instruction clock. use the bit 2 of register w1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. prescaler is initialized, and the output signal (orclk) stops when the bit 3 of register w1 is cleared to 0. (4) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (r1). data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. data can be written to re- load register (r1) with the tr1ab instruction. when writing data to reload register r1 with the tr1ab instruction, the downcount after the underflow is started from the setting value of reload register r1. timer 1 starts counting after the following process; set data in timer 1, and set the bit 1 of register w1 to 1. however, int0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register w1 to 1. when a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes 0), the timer 1 interrupt request flag (t1f) is set to 1, new data is loaded from reload register r1, and count continues (auto-reload function). data can be read from timer 1 with the tab1 instruction. when reading the data, stop the counter and then execute the tab1 in- struction. (5) timer 2 (interrupt function) timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (r2). data can be set simultaneously in timer 2 and the reload register (r2) with the t2ab instruction. timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register w2, and a set the bit 3 of register w2 to 1. when a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes 0), the timer 2 interrupt request flag (t2f) is set to 1, new data is loaded from reload register r2, and count continues (auto-reload function). data can be read from timer 2 with the tab2 instruction. when reading the data, stop the counter and then execute the tab2 in- struction. 25 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (6) timer 3 (interrupt function) timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (r3). data can be set simultaneously in timer 3 and the reload register (r3) with the t3ab instruction. data can be written to re- load register (r3) with the tr3ab instruction. when writing data to reload register r3 with the tr3ab instruc- tion, the downcount after the underflow is started from the setting value of reload register r3. timer 3 starts counting after the following process; set data in timer 3, select the count source with the bits 0 and 1 of register w3, and a set the bit 3 of register w3 to 1. however, int1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register w3 to 1. when a value set is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes 0), the timer 3 interrupt request flag (t3f) is set to 1, new data is loaded from reload register r3, and count continues (auto-reload function). data can be read from timer 3 with the tab3 instruction. when reading the data, stop the counter and then execute the tab3 in- struction. (7) timer 4 (interrupt function) timer 4 is an 8-bit binary down counter with the timer 4 reload reg- ister (r4). data can be set simultaneously in timer 4 and the reload register (r4) with the t4ab instruction. timer 4 starts counting after the following process; set data in timer 4, select the count source with the bits 0 and 1 of register w4, and a set the bit 3 of register w4 to 1. when a value set is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes 0), the timer 4 interrupt request flag (t4f) is set to 1, new data is loaded from reload register r4, and count continues (auto-reload function). data can be read from timer 4 with the tab4 instruction. when reading the data, stop the counter and then execute the tab4 in- struction. (8) timer interrupt request flags (t1f, t2f, t3f, and t4f) each timer interrupt request flag is set to 1 when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2, snzt3, and snzt4). use the interrupt control registers v1, v2 to select an interrupt or a skip instruction. an interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) count start synchronization circuit (timer 1, timer 3) each of timer 1 and timer 3 has the count start synchronous circuit which synchronizes p3 0 /int0 pin and p3 1 /int1 pin, respectively, and can start the timer count operation. timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register w1 to 1. the control by p3 0 /int0 pin input can be performed by setting the bit 0 of register i1 to 1. the count start synchronous circuit is set by level change (h ? l or l ? h) of p3 0 /int0 pin input. this valid waveform is selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1 as follows; ? i1 1 = 0: synchronized with one-sided edge (falling or rising) ? i1 1 = 1: synchronized with both edges (both falling and rising) when register i1 1 =0 (synchronized with the one-sided edge), the ris- ing or falling waveform can be selected by bit 2 of register i1; ? i1 2 = 0: falling waveform ? i1 2 = 1: rising waveform timer 3 count start synchronous circuit function is selected by set- ting the bit 2 of register w3 to 1. the control by p3 1 /int1 pin input can be performed by setting the bit 0 of register i2 to 1. the count start synchronous circuit is set by level change (h ? l or l ? h) of p3 1 /int1 pin input. this valid waveform is selected by bits 1 (i2 1 ) and 2 (i2 2 ) of register i2 as follows; ? i2 1 = 0: synchronized with one-sided edge (falling or rising) ? i2 1 = 1: synchronized with both edges (both falling and rising) when register i2 1 =0 (synchronized with the one-sided edge), the ris- ing or falling waveform can be selected by bit 2 of register i2; ? i2 2 = 0: falling waveform ? i2 2 = 1: rising waveform when timer 1 and timer 3 count start synchronous circuits are used, the count start synchronous circuits are set, the count source is input to each timer by inputting valid waveform to p3 0 /int0 pin and p3 1 /int1 pin. once set, the count start synchronous circuit is cleared by clearing the bit i1 0 or i2 0 to 0 or reset. 26 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. watchdog timer watchdog timer provides a method to reset the system when a pro- gram run-away occurs. watchdog timer consists of a 16-bit timer (wdt), watchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the instruction clocks as the count source after system is released from reset. the underflow signal is generated when the count value reaches 0000 16 . this underflow signal can be used as the timer 2 count source. when the wrst instruction is executed after system is released from reset, the wef flag is set to 1. at this time, the watchdog timer starts operating. when the count value of timer wdt reaches bfff 16 or 3fff 16 , the wdf1 flag is set to 1. if the wrst instruction is never ex- ecuted while timer wdt counts 32767, wdf2 flag is set to 1, and the reset pin outputs l level to reset the microcomputer. ex- ecute the wrst instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the micro- computer operating normally. to prevent the wdt stopping in the event of misoperation, wef flag is designed not to initialize once the wrst instruction has been executed. note also that, if the wrst instruction is never ex- ecuted, the watchdog timer does not start. fig. 20 watchdog timer function the contents of wef, wdf1 and wdf2 flags and timer wdt are initialized at the ram back-up mode. if wdf2 flag is set to 1 at the same time that the microcomputer enters the ram back-up state, system reset may be performed. when using the watchdog timer and the ram back-up mode, ini- tialize the wdf1 flag with the wrst instruction just before the microcomputer enters the ram back-up state (refer to figure 21) fig. 21 program example to enter the ram back-up mode when using the watchdog timer wrst ; wdf1 flag reset ? ? ? pof epof ; pof instruction enabled (ram back-up state) ? ? ? oscillation stop ffff 16 0000 16 3fff 16 bfff 16 the value of timer (wdt) wdf1 flag wdf2 flag wrst instruction executed reset pin output system reset wrst instruction executed wef flag 27 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. serial i/o the 4512 group has a built-in clock synchronous serial i/o which can serially transmit or receive 8-bit data. serial i/o consists of; ? serial i/o register si ? serial i/o mode register j1 ? serial i/o transmission/reception completion flag (siof) ? serial i/o counter registers a and b are used to perform data transfer with internal cpu, and the serial i/o pins are used for external data transfer. the pin functions of the serial i/o pins can be set with the register j1. table 11 serial i/o pins pin p2 0 /s ck p2 1 /s out p2 2 /s in pin function when selecting serial i/o clock i/o (s ck ) serial data output (s out ) serial data input (s in ) note: input ports p2 0 Cp2 2 can be used regardless of register j1. fig. 22 serial i/o structure table 12 serial i/o mode register j1 3 j1 2 j1 1 j1 0 serial i/o mode register j1 this bit has no function, but read/write is enabled. instruction clock signal divided by 8 instruction clock signal divided by 4 input ports p2 0 , p2 1 , p2 2 selected serial i/o ports s ck , s out , s in /input ports p2 0 , p2 1 , p2 2 selected external clock internal clock (instruction clock divided by 4 or 8) not used serial i/o internal clock dividing ratio selection bit serial i/o port selection bit serial i/o synchronous clock selection bit at reset : 0000 2 at ram back-up : state retained note: r represents read enabled, and w represents write enabled. 0 1 0 1 0 1 0 1 r/w j1 2 siof j1 2 j1 1 j1 0 j1 1 j1 0 msb 1/4 1/8 1 0 p2 1 /s out p2 2 /s in p2 0 /s ck tsiab tabsi s out s in s ck j1 3 mr 3 1 0 x in division circuit (divided by 2) internal clock generation circuit (divided by 3) instruction clock serial i/o mode register j1 serial i/o interrupt serial i/o counter (3) synchronous circuit register b (4) register a (4) serial i/o register si (8) lsb note: the output structure of s ck and s out pins is n-channel open-drain. 28 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 23 serial i/o register state when transferring (1) serial i/o register si serial i/o register si is the 8-bit data transfer serial/parallel conver- sion register. data can be set to register si through registers a and b with the tsiab instruction. the contents of register a is transmit- ted to the low-order 4 bits of register si, and the contents of register b is transmitted to the high-order 4 bits of register si. during transmission, each bit data is transmitted lsb first from the lowermost bit (bit 0) of register si, and during reception, each bit data is received lsb first to register si starting from the topmost bit (bit 7). when register si is used as a work register without using serial i/o, pull up the s ck pin or set the pin function to an input port p2 0 . (2) serial i/o transmission/reception completion flag (siof) serial i/o transmission/reception completion flag (siof) is set to 1 when serial data transmission or reception completes. the state of siof flag can be examined with the skip instruction (snzsi). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the siof flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. when transmitting (d 7 Cd 0 : transfer data) when receiving d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s in pin s out pin * s out pin s in pin serial i/o register (si) serial i/o register (si) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 1 d 0 transfer data to be set transfer started transfer completed ******* ******** d 0 ******* ****** ******** d 7 d 6 d 5 d 4 d 3 d 2 ** d 7 d 6 d 5 d 4 d 3 d 2 d 1 * d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (3) serial i/o start instruction (sst) when the sst instruction is executed, the siof flag is cleared to 0 and then serial i/o transmission/reception is started. (4) serial i/o mode register j1 register j1 controls the synchronous clock, p2 0 /s ck , p2 1 /s out and p2 2 /s in pin function. set the contents of this register through register a with the tj1a instruction. the taj1 instruction can be used to transfer the contents of register j1 to register a. 29 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (5) how to use serial i/o figure 24 shows the serial i/o connection example. serial i/o inter- rupt is not used in this example. in the actual wiring, pull up the wiring between each pin with a resistor. figure 25 shows the data transfer timing and table 13 shows the data transfer sequence. fig. 24 serial i/o connection example s out s rdy signal s ck s in d 5 s ck s out s in d 5 master (clock control) serial i/o interrupt enable bit (snzsi instruction is valid) interrupt control register v2 serial i/o mode register j1 serial i/o port s ck, s out, s in instruction clock divided by 8 or 4 selected as a transfer clock internal clock selected as a synchronous clock slave (external clock) 5 0 1 (bit 3) (bit 0) 1 5 5 0 1 55 55 this bit is not valid when j1 0 =? 5 : set an arbitrary value. (bit 3) (bit 0) (bit 3) (bit 0) (bit 3) (bit 0) 0 555 serial i/o interrupt enable bit (snzsi instruction is valid) interrupt control register v2 serial i/o port s ck, s out, s in external clock selected as a synchronous clock serial i/o mode register j1 30 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. fig. 25 timing of serial i/o data transfer s in s out s out s in s 0 s 7 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 0 s 7 s 1 s 3 s 4 s 5 s 6 s 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 s 2 m 0 Cm 7 : the contents of master serial i/o register s 0 Cs 7 : the contents of slave serial i/o register rising of s ck : serial input falling of s ck : serial output master slave sst instruction sst instruction s rdy signal s ck 31 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 13 processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. subsequently, data can be transferred continuously by repeating the process from *. when an external clock is selected as a synchronous clock, the clock is not controlled internally. control the clock externally be- cause serial transfer is performed as long as clock is externally input. (unlike an internal clock, an external clock is not stopped when serial transfer is completed.) however, the siof flag is set to 1 when the clock is counted 8 times after executing the sst in- struction. be sure to set the initial level of the external clock to h. master (transmission) [initial setting] ? setting the serial i/o mode register j1 and inter- rupt control register v2 shown in figure 24. tj1a and tv2a instructions ? setting the port received the reception enable signal (s rdy ) to the input mode. (port d 5 is used in this example) sd instruction * [transmission enable state] ? storing transmission data to serial i/o register si. tsiab instruction [transmission] ?check port d 5 is l level. szd instruction ?serial transfer starts. sst instruction ?check transmission completes. snzsi instruction ?wait (timing when continuously transferring) slave (reception) [initial setting] ? setting serial i/o mode register j1, and interrupt control register v2 shown in figure 24. tj1a and tv2a instructions ? setting the port transmitted the reception enable signal (s rdy ) and outputting h level (reception impossible). (port d 5 is used in this example) sd instruction *[reception enable state] ? the siof flag is cleared to 0. sst instruction ? l level (reception possible) is output from port d 5 . rd instruction [reception] ? check reception completes. snzsi instruction ? h level is output from port d 5 . sd instruction [data processing] 32 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. a-d converter the 4512 group has a built-in a-d conversion circuit that performs conversion by 10-bit successive comparison method. t able 14 shows the characteristics of this a-d converter . this a-d converter can also be used as an 8-bit comparator to compare analog vo lt- ages input from the analog input pin with preset values. t able 14 a-d converter characteristics characteristics successive comparison method 10 bits linearity error: 2lsb non-linearity error: 0.9lsb 46.5 m s (high-speed mode at 4.0 mhz oscillation frequency) 4 parameter conversion format resolution relative accuracy conversion speed analog input pin fig. 26 a-d conversion circuit structure v ss v dd t abad 1/ 6 q2 3 q1 1 q1 0 q1 2 ta d a b q2 2 q2 1 q2 0 0 1 4 4 4 4 8 8 8 0 1 8 10 q2 3 q2 3 0 1 q2 3 8 8 2 ta l a q2 3 q1 3 ta q 1 tq 1 a ta q 2 tq 2 a ad f ( 1) a i n0 3 1 0 10 a i n1 a i n2 a i n3 register a (4) register b (4) dac operation signal comparator 4-channel multi-plexed analog switch instruction clock a-d control circuit successive comparison register (ad) (10) a-d interrupt da converter ( note 1 ) comparator register (8) ( note 2 ) notes 1: this switch is turned on only when a-d converter is operati ng and generates the comparison voltage. 2: writing/reading data to the comparator register is possible only in the comparator mode (q2 3 =1). the value of the comparator register is retained even when t he mode is switched to the a-d conversion mode (q2 3 =0) because it is separated from the successive comparison r egister (ad). also, the resolution in the comparator mode is 8 bits because the comparator regist er consists of 8 bits. 1 33 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. q1 3 q1 2 q1 1 q1 0 a-d control register q1 not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 q1 2 0 0 0 0 1 1 1 1 q1 1 0 0 1 1 0 0 1 1 this bit has no function, but read/write is enabled. selected pins a in0 a in1 a in2 a in3 not available not available not available not available at reset : 0000 2 q2 3 q2 2 q2 1 q2 0 a-d control register q2 a-d conversion mode comparator mode this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. a-d operation mode selection bit not used not used not used at ram back-up : state retained 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. q1 0 0 1 0 1 0 1 0 1 (1) operating at a-d conversion mode the a-d conversion mode is set by setting the bit 3 of register q2 to 0. (2) successive comparison register ad register ad stores the a-d conversion result of an analog input in 10-bit digital data format. the contents of the high-order 8 bits of this register can be stored in register b and register a with the tabad instruction. the contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register a with the tala instruction. however, do not execute this instruction during a- d conversion. when the contents of register ad is n, the logic value of the com- parison voltage v ref generated from the built-in da converter can be obtained with the reference voltage v dd by the following for- mula: logic value of comparison voltage v ref v ref = 5 n n: the value of register ad (n = 0 to 1023) v dd 1024 (4) a-d conversion start instruction (adst) a-d conversion starts when the adst instruction is executed. the conversion result is automatically stored in the register ad. (5) a-d control register q1 register q1 is used to select one of analog input pins. (6) a-d control register q2 register q2 controls the a-d conversion mode. the a-d conver- sion mode is selected when the bit 3 of register q2 is 0, and the comparator mode is selected when the bit 3 of register q2 is 1. r/w r/w table 15 a-d control registers (3) a-d conversion completion flag (adf) a-d conversion completion flag (adf) is set to 1 when a-d con- version completes. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the interrupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. 34 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 16 change of successive comparison register ad during a-d conversion comparison voltage (v ref ) value change of successive comparison register ad at starting conversion (7) operation description a-d conversion is started with the a-d conversion start instruction (adst). the internal operation during a-d conversion is as follows: ? when a-d conversion starts, the register ad is cleared to 000 16 . ? next, the topmost bit of the register ad is set to 1, and the comparison voltage v ref is compared with the analog input volt- age v in . ? when the comparison result is v ref < v in , the topmost bit of the register ad remains set to 1. when the comparison result is v ref > v in , it is cleared to 0. the 4512 group repeats this operation to the lowermost bit of the register ad to convert an analog value to a digital value. a-d con- version stops after 62 machine cycles (46.5 m s when f(x in ) = 4.0 mhz in high-speed mode) from the start, and the conversion result is stored in the register ad. an a-d interrupt activated condition is satisfied and the adf flag is set to 1 as soon as a-d conversion completes (figure 27). \ 1: 1st comparison result \ 3: 3rd comparison result \ 9: 9th comparison result \ 2: 2nd comparison result \ 8: 8th comparison result \ a: 10th comparison result 1st comparison 2nd comparison 3rd comparison after 10th comparison completes 1 \ 1 \ 1 \ 1 ----- ----- ----- ----- 0 1 \ 2 \ 2 0 0 1 \ 3 0 0 0 \ 8 0 0 0 \ 9 0 0 0 \ a a-d conversion result v dd 2 v dd 2 v dd 2 v dd 2 v dd 4 v dd 4 v dd 8 v dd 1024 ------------- ------------- ------------- ------------- ------------- ------------- ------------- ------------- (8) a-d conversion timing chart figure 27 shows the a-d conversion timing chart. fig. 27 a-d conversion timing chart adst instruction a-d conversion completion flag (adf) 62 machine cycles dac operation signal 35 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (9) operation at comparator mode the a-d converter is set to comparator mode by setting bit 3 of the register q2 to 1. below, the operation at comparator mode is described. (10) comparator register in comparator mode, the built-in da comparator is connected to the comparator register as a register for setting comparison voltages. the contents of register b is stored in the high-order 4 bits of the comparator register and the contents of register a is stored in the low-order 4 bits of the comparator register with the tadab instruc- tion. when changing from a-d conversion mode to comparator mode, the result of a-d conversion (register ad) is undefined. however, because the comparator register is separated from regis- ter ad, the value is retained even when changing from comparator mode to a-d conversion mode. note that the comparator register can be written and read at only comparator mode. if the value in the comparator register is n, the logic value of com- parison voltage v ref generated by the built-in da converter can be determined from the following formula: (11) comparison result store flag (adf) in comparator mode, the adf flag, which shows completion of a-d conversion, stores the results of comparing the analog input volt- age with the comparison voltage. when the analog input voltage is lower than the comparison voltage, the adf flag is set to 1. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) comparator operation start instruction (adst instruction) (figure 28) in comparator mode, executing adst starts the comparator oper- ating. the comparator stops 8 machine cycles after it has started (6 m s at f(x in ) = 4.0 mhz in high-speed mode). when the analog input volt- age is lower than the comparison voltage, the adf flag is set to 1. (13) notes for the use of a-d conversion 1 ? tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. (14) notes for the use of a-d conversion 2 do not change the operating mode (both a-d conversion mode and comparator mode) of a-d converter with bit 3 of register q2 while a-d converter is operating. when the operating mode of a-d converter is changed from the comparator mode to a-d conversion mode with the bit 3 of register q2, note the following; ? clear bit 2 of register v2 to 0 to change the operating mode of the a-d converter from the comparator mode to a-d conversion mode with the bit 3 of register q2. ? the a-d conversion completion flag (adf) may be set when the operating mode of the a-d converter is changed from the com- parator mode to the a-d conversion mode. accordingly, set a value to register q2, and execute the snzad instruction to clear the adf flag. logic value of comparison voltage v ref v ref = 5 n n: the value of register ad (n = 0 to 255) fig. 28 comparator operation timing chart v dd 256 adst instruction comparison result store flag(adf) 8 machine cycles dac operation signal comparator operation completed. ( th e v a l ue o f adf i s de t e rmin ed) 36 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (15) definition of a-d converter accuracy the a-d conversion accuracy is defined below (refer to figure 29). ? relative accuracy ? zero transition voltage (v 0t ) this means an analog input voltage when the actual a-d con- version output data changes from 0 to 1. ? full-scale transition voltage (v fst ) this means an analog input voltage when the actual a-d con- version output data changes from 1023 to 1022. ? linearity error this means a deviation from the line between v 0t and v fst of a converted value between v 0t and v fst . differential non-linearity error this means a deviation from the input potential difference re- quired to change a converter value between v 0t and v fst by 1 lsb at the relative accuracy. ? absolute accuracy this means a deviation from the ideal characteristics between 0 to v dd of actual a-d conversion characteristics. fig. 29 definition of a-d conversion accuracy vn: analog input voltage when the output data changes from n to n+1 (n = 0 to 1022) ? 1lsb at relative accuracy ? (v) ? 1lsb at absolute accuracy ? (v) v fst Cv 0t 1022 v dd 1024 v dd v 1022 v n v 1 v 0 v n+1 n+1 n 1022 1023 1 0 b a c output data differential non-linearity error = linearity error = [lsb] c a b? a [lsb] actual a-d conversion characteristics a: 1lsb by relative accuracy b: v n+1 ? n c: difference between ideal v n and actual v n zero transition voltage (v 0t ) analog voltage full-scale transition voltage (v fst ) ideal line of a-d conversion between v 0 ? 1022 37 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. reset function system reset is performed by applying l level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. then when h level is applied to reset pin, software starts from address 0 in page 0. fig. 30 reset release timing fig. 31 reset pin input waveform and reset operation f(x in ) reset software starts (address 0 in page 0) f(x in ) is counted 16892 to 16895 times. ( note ) note: it depends on the internal state of the microcomputer when reset is performed. reset 0.3v dd 0.85v dd software starts (address 0 in page 0) f(x in ) is counted 16892 to 16895 times. ( note ) note: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. reset input 1 machine cycle or more = 38 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. (1) power-on reset reset can be performed automatically at power on (power-on r e- set) by connecting resistors, a diode, and a capacitor to reset pin. connect reset pin and the external circuit at the short est dis- tance. fig. 32 power-on reset circuit example (2) internal state at reset t able 17 shows port state at reset, and figure 33 shows inter nal state at reset (they are the same after system is released f rom re- set). the contents of timers, registers, flags and ram except shown in figure 33 are undefined, so set the initial value t o them. t able 17 port state at reset name d 0 ed 7 p0 0 ep0 3 p1 0 ep1 3 p2 0 /s ck , p2 1 /s out , p2 2 /s in notes 1: output latch is set to 1. 2: pull-up transistor is turned off. function d 0 ed 7 p0 0 ep0 3 p1 0 ep1 3 p2 0 ep2 2 state high impedance (note 1) high impedance (notes 1, 2) high impedance v dd reset pin wef ( note ) internal reset signal watchdog timer output v dd reset pin voltage power-on reset released internal reset signal reset state note: this symbol represents a parasitic diode. applied potential to reset pin must be v dd or less. 39 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. ? program counter (pc) ......................................................................................................... . address 0 in page 0 is set to program counter. ? interrupt enable flag (inte) ................................................................................................. . ? power down flag (p) .......................................................................................................... ... ? external 0 interrupt request flag (exf0) .............................................................................. ? external 1 interrupt request flag (exf1) .............................................................................. ? interrupt control register v1 ................................................................................................ .. ? interrupt control register v2 ................................................................................................ .. ? interrupt control register i1 ................................................................................................ ... ? interrupt control register i2 ................................................................................................ ... ? timer 1 interrupt request flag (t1f) ..................................................................................... ? timer 2 interrupt request flag (t2f) ..................................................................................... ? timer 3 interrupt request flag (t3f) ..................................................................................... ? timer 4 interrupt request flag (t4f) ..................................................................................... ? watchdog timer flags (wdf1, wdf2) .................................................................................. ? watchdog timer enable flag (wef) ...................................................................................... ? timer control register w1 .................................................................................................... . ? timer control register w2 .................................................................................................... . ? timer control register w3 .................................................................................................... . ? timer control register w4 .................................................................................................... . ? clock control register mr .................................................................................................... . ? serial i/o transmission/reception completion flag (siof) ................................................... ? serial i/o mode register j1 .................................................................................................. ? serial i/o register si ....................................................................................................... ...... ? a-d conversion completion flag (adf) ................................................................................. ? a-d control register q1 ...................................................................................................... ... ? a-d control register q2 ...................................................................................................... ... ? successive comparison register ad .................................................................................... ? comparator register .......................................................................................................... .... ? key-on wakeup control register k0 ...................................................................................... ? pull-up control register pu0 ................................................................................................. ? carry flag (cy) .............................................................................................................. ........ ? register a ................................................................................................................... .......... ? register b ................................................................................................................... .......... ? register d ................................................................................................................... .......... ? register e ................................................................................................................... .......... ? register x ................................................................................................................... .......... ? register y ................................................................................................................... .......... ? register z ................................................................................................................... .......... ? stack pointer (sp) ........................................................................................................... ..... 5 represents undefined. fig. 33 internal state at reset 55 5555 55 55 (external clock selected and serial i/o port not selected) 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0000 0000 0 0 0 0 0 0 0 0 0 0 (prescaler and timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0 0 0 0 (timer 3 stopped) 0 0 0 0 (timer 4 stopped) 1000 0 0000 555555 0 0000 0000 555555 555555 0000 0000 0 0000 0000 555 555555 0000 0000 55 111 40 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. ram back-up mode the 4512 group has the ram back-up mode. when the epof and pof instructions are executed continuously, system enters the ram back-up state. the pof instruction is equal to the nop instruction when the epof instruction is not ex- ecuted before the pof instruction. as oscillation stops retaining ram, the function of reset circuit and states at ram back-up mode, current dissipation can be reduced without losing the contents of ram. table 18 shows the function and states retained at ram back-up. figure 34 shows the state transition. (1) identification of the start condition warm start (return from the ram back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the power down flag (p) with the snzp instruction. (2) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the epof and pof instruc- tions continuously, the cpu starts executing the program from address 0 in page 0. in this case, the p flag is 1. (3) cold start condition the cpu starts executing the program from address 0 in page 0 when; ? reset pulse is input to reset pin, or ? reset by watchdog timer is performed, or in this case, the p flag is 0. table 18 functions and states retained at ram back-up function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram port level timer control register w1 timer control registers w2 to w4 clock control register mr interrupt control registers v1, v2 interrupt control registers i1, i2 timer 1 function timer 2 function timer 3 function timer 4 function a-d conversion function a-d control registers q1, q2 serial i/o function serial i/o mode register j1 pull-up control register pu0 key-on wakeup control register k0 external 0 interrupt request flag (exf0) external 1 interrupt request flag (exf1) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) timer 3 interrupt request flag (t3f) timer 4 interrupt request flag (t4f) watchdog timer flags (wdf1, wdf2) watchdog timer enable flag (wef) 16-bit timer (wdt) a-d conversion completion flag (adf) serial i/o transmission/reception completion flag (siof) interrupt enable flag (inte) ram back-up 5 o o 5 o 5 5 o 5 (note 3) (note 3) (note 3) 5 o 5 o o o 5 5 5 (note 3) (note 3) (note 3) 5 (note 4) 5 (note 4) 5 (note 4) 5 5 5 notes 1: o represents that the function can be retained, and 5 repre- sents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 7 at ram back-up. 3: the state of the timer is undefined. 4: initialize the watchdog timer with the wrst instruction, and then execute the pof instruction. 41 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (4) return signal an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 19 shows the return condition for each return source. table 19 return source and return condition remarks set the port using the key-on wakeup function selected with register k0 to h level before going into the ram back-up state because the port p0 shares the falling edge detection circuit with port p1. select the return level (l level or h level) with the bit 2 of register i1 ac- cording to the external state before going into the ram back-up state. select the return level (l level or h level) with the bit 2 of register i2 ac- cording to the external state before going into the ram back-up state. return condition return by an external falling edge input (h ? l). return by an external h level or l level input. the exf0 flag is not set. return by an external h level or l level input. the exf1 flag is not set. external wakeup signal return source ports p0, p1 int0 pin int1 pin fig. 34 state transition fig. 35 set source and clear source of the p flag fig. 36 start condition identified example using the snzp in- struction : time required to stabilize the f(x in ) oscillation is automatically generated by hardware. stabilizing time a pof instruction is executed a f(x in ) oscillation return input (stabilizing time a ) b (ram back-up mode) f(x in ) stop reset (stabilizing time a ) software start p = ? ? yes warm start cold start no (5) ports p0 and p1 control registers ? key-on wakeup control register k0 register k0 controls the ports p0 and p1 key-on wakeup func- tion. set the contents of this register through register a with the tk0a instruction. in addition, the tak0 instruction can be used to transfer the contents of register k0 to register a. ? pull-up control register pu0 register pu0 controls the on/off of the ports p0 and p1 pull- up transistor. set the contents of this register through register a with the tpu0a instruction. in addition, the tapu0 instruction can be used to transfer the contents of register pu0 to register a. s r q power down flag p pof instruction reset input l set source pof instruction is executed l clear source reset input ??? ? ?? ? 42 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. table 20 key-on wakeup control register, pull-up control register, and interrupt control register k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 pu0 3 pu0 2 pu0 1 pu0 0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used pins p1 2 and p1 3 key-on wakeup control bit pins p1 0 and p1 1 key-on wakeup control bit pins p0 2 and p0 3 key-on wakeup control bit pins p0 0 and p0 1 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pins p1 2 and p1 3 pull-up transistor control bit pins p1 0 and p1 1 pull-up transistor control bit pins p0 2 and p0 3 pull-up transistor control bit pins p0 0 and p0 1 pull-up transistor control bit r/w pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w i1 3 i1 2 i1 1 i1 0 i2 3 i2 2 i2 1 i2 0 not used interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 control enable bit this bit has no function, but read/write is enabled. falling waveform (l level of int1 pin is recognized with the snzi1 instruction)/l level rising waveform (h level of int1 pin is recognized with the snzi1 instruction)/h level one-sided edge detected both edges detected disabled enabled not used interrupt valid waveform for int1 pin/ return level selection bit (note 3) int1 pin edge detection circuit control bit int1 pin timer 3 control enable bit notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 is changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 instruction. 3: when the contents of i2 2 is changed, the external interrupt request flag exf1 may be set. accordingly, clear exf1 flag with the snz1 instruction. interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. falling waveform (l level of int0 pin is recognized with the snzi0 instruction)/l level rising waveform (h level of int0 pin is recognized with the snzi0 instruction)/h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 interrupt control register i2 r/w at ram back-up : state retained at reset : 0000 2 43 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. clock control the clock control circuit consists of the following circuits. ? system clock generating circuit ? control circuit to stop the clock oscillation fig. 37 clock control circuit structure (1) clock control register register mr controls system clock. set the contents of this regis- ter through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 23 clock control register mr note : r represents read enabled, and w represents write enabled. ? control circuit to switch the middle-speed mode and high-speed mode ? control circuit to return from the ram back-up state mr 3 mr 2 mr 1 mr 0 clock control register mr f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. system clock selection bit not used not used not used at reset : 1000 2 at ram back-up : 1000 2 0 1 0 1 0 1 0 1 r/w instruction clock mr 3 1 0 reset falling detected ports p0 0 , p0 1 ports p0 2 , p0 3 ports p1 0 , p1 1 ports p1 2 , p1 3 multi- plexer k0 0 ,k0 1 ,k0 2 ,k0 3 counter wait time (note) control circuit software start signal r s q pof instruction x in x out i1 2 0 ??level 1 int0 key-on wake up control register i2 2 0 1 int1 oscillation circuit division circuit (divided by 2) internal clock generation circuit (divided by 3) ??level ??level ??level note: the wait time control circuit is used to generate the time required to stabilize the f(x in ) oscillation. system clock 44 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. clock signal f(x in ) is obtained by externally connecting a ceramic resonator. connect this external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in between pins x in and x out . when an external clock signal is input, connect the clock source to x in and leave x out open. when using an external clock, the maxi- mum value of external clock oscillating frequency is shown in table 22. table 22 maximum value of external clock oscillation frequency supply voltage v dd = 4.0 v to 5.5 v oscillation frequency (duty ratio) 3.0 mhz (40 % to 60 %) rom ordering method please submit the information described below when ordering mask rom. (1) mask rom order confirmation form ..................................... 1 (2) data to be written into mask rom ............................... eprom (three sets containing the identical data) (3) mark specification form .......................................................... 1 fig. 38 ceramic resonator external circuit fig. 39 external clock input circuit note: externally connect a damping resistor rd de- pending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturers recommended value because constants such as capacitance de- pend on the resonator. 4512 x in x out rd c in c out 4512 x in x out external oscillation circuit v dd v ss 45 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. differences from 4513 group the 4512 group has pin-compatibility with the 4513 group, bu t its function and recommended operating condition are dif ferent from the 4513 group. the dif ferences are as follows: basic instructions v oltage drop detection circuit v oltage comparator t imer i/o (cntr0, cntr1) ports p3 0 , p3 1 t imer control register w6 v oltage comparator control register w6 supply voltage large size memory version supported dip package supported one t ime prom version supported hardware recommended operating condition others 4513 group 123 o o o o o o 2.5 v to 5.5 v 2.0 v to 5.5 v 4.0 v to 5.5 v 2.5 v to 5.5 v 2.0 v to 5.5 v o (m34513m6/m8/e8) o (m34513m2/m4/e4) o (m34513e4/e8) 4512 group 1 17 (note 2) 5 5 5 5 5 5 4.0 v to 5.5 v 5 5 5 (m34513e4 can be used) parameter pin configura tions 4513 group 4512 group pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4513 group d 3 d 4 d 5 d 6 /cntr0 d 7 /cntr1 p2 0 /s ck p2 1 /s out p2 2 /s in reset cnv ss x out x in v ss v dd vdce p3 0 /int0 p3 1 /int1 a in0 /cmp0- a in1 /cmp0+ a in2 /cmp1- a in3 /cmp1+ p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 d 0 d 1 d 2 4512 group d 3 d 4 d 5 d 6 d 7 p2 0 /s ck p2 1 /s out p2 2 /s in reset cnv ss x out x in v ss v dd n.f int0 int1 a in0 a in1 a in2 a in3 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 d 0 d 1 d 2 notes 1: o represents that the function is supported, 5 represents that the function is not supported. 2: for the 4512 group, tq3a, t aq3, tw6a, t a w6, op3a and iap3 instructions cannot be used. 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 m34513mx-xxxfp m34513exfp 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 d 2 d 1 d 0 p1 3 p1 2 p1 1 p1 0 p0 3 reset cnv ss x out x in v ss v dd vdce p3 0 /int0 d 3 d 4 d 5 d 6 /cntr 0 d 7 /cntr 1 p2 0 /s ck p2 1 /s out p2 2 /s in p0 2 p0 1 p0 0 a in3 /cmp1+ a in2 /cmp1- a in1 /cmp0+ a in0 /cmp0- p3 1 /int1 m34512mx-xxxfp 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 p0 2 p0 1 p0 0 a in3 a in2 a in1 a in0 int1 d 3 d 4 d 5 d 6 d 7 p2 0 /s ck p2 1 /s out p2 2 /s in d 2 d 1 d 0 p1 3 p1 2 p1 1 p1 0 p0 3 reset cnv ss x out x in v ss v dd n.f int0 46 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. list of precautions noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; ? connect a bypass capacitor (approx. 0.1 m f) between pins v dd and v ss at the shortest distance, ? equalize its wiring in width and length, and ? use relatively thick wire. prescaler stop the prescaler operation to change its frequency dividing ra- tio. a timer count source stop timer 1, 2, 3, or 4 counting to change its count source. ? reading the count value stop timer 1, 2, 3, or 4 counting and then execute the tab1, tab2, tab3, or tab4 instruction to read its data. ? writing to reload registers r1 and r3 when writing data to reload registers r1 or r3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. ? int0 pin when the interrupt valid waveform of the int0 pin is changed with the bit 2 of register i1 in software, be careful about the fol- lowing notes. ? clear the bit 0 of register v1 to 0 before the interrupt valid wave- form of int0 pin is changed with the bit 2 of register i1 (refer to figure 40 ). ? depending on the input state of the int0 pin, the external 0 inter- rupt request flag (exf0) may be set when the interrupt valid waveform is changed. accordingly, clear bit 2 of register i1, and execute the snz0 instruction to clear the exf0 flag after execut- ing at least one instruction (refer to figure 40 ) fig. 41 external 1 interrupt program example ? multifunction the input of p2 0 Cp2 2 can be used even when s ck , s out , s in are selected. ? int1 pin when the interrupt valid waveform of int1 pin is changed with the bit 2 of register i2 in software, be careful about the following notes. ? clear the bit 1 of register v1 to 0 before the interrupt valid wave- form of int1 pin is changed with the bit 2 of register i2 (refer to figure 41 a ). ? depending on the input state of the int1 pin, the external 1 inter- rupt request flag (exf1) may be set when the interrupt valid waveform is changed. accordingly, clear bit 2 of register i2 and execute the snz1 instruction to clear the exf1 flag after execut- ing at least one instruction (refer to figure 41 ? ). la 8 ; ( 55 0 5 2 ) tv1a ; the snz1 instruction is valid ........... a la 8 ti2a ; change of the interrupt valid waveform nop ........................................................... ? snz1 ; the snz1 instruction is executed nop 5 : this bit is not related to the setting of int1. . . . . . . la 4 ; ( 555 0 2 ) tv1a ; the snz0 instruction is valid ........... la 4 ; ti1a ; interrupt valid waveform is changed nop ........................................................... snz0 ; the snz0 instruction is executed nop 5 : this bit is not related to the setting of int0 pin. . . . . . . fig. 40 external 0 interrupt program example 47 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter-1 when the operating mode of the a-d converter is changed from the comparator mode to the a-d conversion mode with the bit 3 of register q2 in a program, be careful about the following notes. ? clear the bit 2 of register v2 to 0 to change the operating mode of the a-d converter from the comparator mode to the a-d con- version mode with the bit 3 of register q2 (refer to figure 42 ? ). ? the a-d conversion completion flag (adf) may be set when the operating mode of the a-d converter is changed from the com- parator mode to the a-d conversion mode. accordingly, set a value to register q2, and execute the snzad instruction to clear the adf flag. do not change the operating mode (both a-d conversion mode and comparator mode) of a-d converter with the bit 3 of register q2 during operating the a-d converter. . . . la 8 ; ( 5 0 55 2 ) tv2a ; the snzad instruction is valid ........ ? la 0 ; (0 555 2 ) tq2a ; change of the operating mode of the a-d converter from the comparator mode to the a-d conversion mode snzad nop . . . fig. 43 analog input external circuit example-1 fig. 44 analog input external circuit example-2 pof instruction execute the pof instruction immediately after executing the epof instruction to enter the ram back-up. note that system cannot enter the ram back-up state when ex- ecuting only the pof instruction. be sure to disable interrupts by executing the di instruction be- fore executing the epof instruction. tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. program counter make sure that the pc h does not specify after the last page of the built-in rom. n.f pin this pin has no function, and connect to v ss as an unused pin. a-d converter-2 each analog input pin is equipped with a capacitor which is used to compare the analog voltage. accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient a-d accuracy may not be obtained. therefore, reduce the impedance or, con- nect a capacitor (0.01 m f to 1 m f) to analog input pins (figure 43). when the overvoltage applied to the a-d conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the figure 44. in addition, test the application products sufficiently. 5 : this bit is not related to the change of the operating mode of the a-d conversion. fig. 42 a-d converter operating mode program example 11 12 13 14 sensor a in apply the voltage withiin the specifications to an analog input pin. sensor a in about 1k w 48 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. control registers v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 serial i/o interrupt enable bit a-d interrupt enable bit timer 4 interrupt enable bit timer 3 interrupt enable bit interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) interrupt disabled (snzsi instruction is valid) interrupt enabled (snzsi instruction is invalid) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) interrupt disabled (snzt4 instruction is valid) interrupt enabled (snzt4 instruction is invalid) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 interrupt control register v2 r/w at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 i1 3 i1 2 i1 1 i1 0 i2 3 i2 2 i2 1 i2 0 not used interrupt valid waveform for int0 pin/ return level selection bit (note 2) int0 pin edge detection circuit control bit int0 pin timer 1 control enable bit this bit has no function, but read/write is enabled. falling waveform (l level of int1 pin is recognized with the snzi1 instruction)/l level rising waveform (h level of int1 pin is recognized with the snzi1 instruction)/h level one-sided edge detected both edges detected disabled enabled not used interrupt valid waveform for int1 pin/ return level selection bit (note 3) int1 pin edge detection circuit control bit int1 pin timer 3 control enable bit notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 is changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 instruction. 3: when the contents of i2 2 is changed, the external interrupt request flag exf1 may be set. accordingly, clear exf1 flag with the snz1 instruction. interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. falling waveform (l level of int0 pin is recognized with the snzi0 instruction)/l level rising waveform (h level of int0 pin is recognized with the snzi0 instruction)/h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 interrupt control register i2 r/w at ram back-up : state retained at reset : 0000 2 49 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating this bit has no function, but read/write is enabled. count source timer 1 underflow signal prescaler output not available 16 bit timer (wdt) underflow signal timer 2 control bit not used timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 w2 3 w2 2 w2 1 w2 0 w3 3 w3 2 w3 1 w3 0 w4 3 w4 2 w4 1 w4 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 w3 1 0 0 1 1 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected count source timer 2 underflow signal prescaler output not available not available timer 3 control bit timer 3 count start synchronous circuit control bit timer 3 count source selection bits 0 1 0 1 w3 0 0 1 0 1 timer control register w3 r/w at ram back-up : state retained at reset : 0000 2 w4 1 0 0 1 1 stop (state retained) operating this bit has no function, but read/write is enabled. count source timer 3 underflow signal prescaler output not available not available timer 4 control bit not used timer 4 count source selection bits 0 1 0 1 w4 0 0 1 0 1 timer control register w4 r/w at ram back-up : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled. control registers (continued) 50 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. control registers (continued) j1 3 j1 2 j1 1 j1 0 serial i/o mode register j1 this bit has no function, but read/write is enabled. instruction clock signal divided by 8 instruction clock signal divided by 4 input ports p2 0 , p2 1 , p2 2 selected serial i/o ports s ck , s out , s in /input ports p2 0 , p2 1 , p2 2 selected external clock internal clock (instruction clock divided by 4 or 8) not used serial i/o internal clock dividing ratio selection bit serial i/o port selection bit serial i/o synchronous clock selection bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w q1 3 q1 2 q1 1 q1 0 a-d control register q1 not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 q1 2 0 0 0 0 1 1 1 1 q1 1 0 0 1 1 0 0 1 1 this bit has no function, but read/write is enabled. selected pins a in0 a in1 a in2 a in3 not available not available not available not available at reset : 0000 2 q2 3 q2 2 q2 1 q2 0 a-d control register q2 a-d conversion mode comparator mode this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. a-d operation mode selection bit not used not used not used at ram back-up : state retained 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. q1 0 0 1 0 1 0 1 0 1 r/w r/w 51 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 pu0 3 pu0 2 pu0 1 pu0 0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used pins p1 2 and p1 3 key-on wakeup control bit pins p1 0 and p1 1 key-on wakeup control bit pins p0 2 and p0 3 key-on wakeup control bit pins p0 0 and p0 1 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pins p1 2 and p1 3 pull-up transistor control bit pins p1 0 and p1 1 pull-up transistor control bit pins p0 2 and p0 3 pull-up transistor control bit pins p0 0 and p0 1 pull-up transistor control bit r/w pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w control registers (continued) note : r represents read enabled, and w represents write enabled. mr 3 mr 2 mr 1 mr 0 clock control register mr f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. system clock selection bit not used not used not used at reset : 1000 2 at ram back-up : 1000 2 0 1 0 1 0 1 0 1 r/w 52 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. symbol the symbols shown below are used in the following instruction function table and instruction list. symbol a b dr e q1 q2 ad j1 si v1 v2 i1 i2 w1 w2 w3 w4 mr k0 pu0 x y z dp pc pc h pc l sk sp cy r1 r2 r3 r4 t1 t2 t3 t4 contents register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) a-d control register q1 (4 bits) a-d control register q2 (4 bits) successive comparison register ad (10 bits) serial i/o mode register j1 (4 bits) serial i/o register si (8 bits) interrupt control register v1 (4 bits) interrupt control register v2 (4 bits) interrupt control register i1 (4 bits) interrupt control register i2 (4 bits) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w3 (4 bits) timer control register w4 (4 bits) clock control register mr (4 bits) key-on wakeup control register k0 (4 bits) pull-up control register pu0 (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits 5 8) stack pointer (3 bits) carry flag timer 1 reload register timer 2 reload register timer 3 reload register timer 4 reload register timer 1 timer 2 timer 3 timer 4 contents timer 1 interrupt request flag timer 2 interrupt request flag timer 3 interrupt request flag timer 4 interrupt request flag watchdog timer flag watchdog timer enable flag interrupt enable flag external 0 interrupt request flag external 1 interrupt request flag power down flag a-d conversion completion flag serial i/o transmission/reception completion flag port d (8 bits) port p0 (4 bits) port p1 (4 bits) port p2 (3 bits) hexadecimal variable hexadecimal variable hexadecimal variable hexadecimal variable hexadecimal constant hexadecimal constant hexadecimal constant binary notation of hexadecimal variable a (same for others) direction of data movement data exchange between a register and memory decision of state shown before ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 5 p 4 p 3 p 2 p 1 p 0 hex. c + hex. number x (also same for others) symbol t1f t2f t3f t4f wdf1, wdf2 wef inte exf0 exf1 p adf siof d p0 p1 p2 x y z p n i j a 3 a 2 a 1 a 0 ? ? ? ( ) m(dp) a p, a c + x note : the 4512 group just invalidates the next instruction when a skip is performed. the contents of program counter is not inc reased by 2. accordingly, the number of cycles does not change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. 53 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. list of instruction function group- ing ram addresses function (mj(dp)) ? 1 j = 0 to 3 (mj(dp)) ? 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? n = 0 to 15 (pc l ) ? a 6 Ca 0 (pc h ) ? p (pc l ) ? a 6 Ca 0 (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? 2 (pc l ) ? a 6 Ca 0 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? a 6 Ca 0 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (pc) ? (sk(sp)) (sp) ? (sp) C 1 comparison operation subroutine operation branch operation bit operation return operation mnemonic sb j rb j szb j seam sea n b a bl p, a bla p bm a bml p, a bmla p rti rt rts mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar function (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) + 1 (m(dp)) ? (a) (x) ? (x)exor(j) j = 0 to 15 (a) ? n n = 0 to 15 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 Cdr 0 , a 3 Ca 0 ) (b) ? (rom(pc)) 7 C 4 (a) ? (rom(pc)) 3 C 0 (pc) ? (sk(sp)) (sp) ? (sp) C 1 (a) ? (a) + (m(dp)) (a) ? (a) + (m(dp)) + (cy) (cy) ? carry (a) ? (a) + n n = 0 to 15 (a) ? (a) and (m(dp)) (a) ? (a) or (m(dp)) (cy) ? 1 (cy) ? 0 (cy) = 0 ? (a) ? (a) ? cy ? a 3 a 2 a 1 a 0 mnemonic tab tba tay tya teab tabe tda tad taz tax tasp lxy x, y lz z iny dey tam j xam j xamd j function (a) ? (b) (b) ? (a) (a) ? (y) (y) ? (a) (e 7 Ce 4 ) ? (b) (e 3 Ce 0 ) ? (a) (b) ? (e 7 Ce 4 ) (a) ? (e 3 Ce 0 ) (dr 2 Cdr 0 ) ? (a 2 Ca 0 ) (a 2 Ca 0 ) ? (dr 2 Cdr 0 ) (a 3 ) ? 0 (a 1 , a 0 ) ? (z 1 , z 0 ) (a 3 , a 2 ) ? 0 (a) ? (x) (a 2 Ca 0 ) ? (sp 2 Csp 0 ) (a 3 ) ? 0 (x) ? x, x = 0 to 15 (y) ? y, y = 0 to 15 (z) ? z, z = 0 to 3 (y) ? (y) + 1 (y) ? (y) C 1 (a) ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (a) ? ? (m(dp)) (x) ? (x)exor(j) j = 0 to 15 (y) ? (y) C 1 ram to register transfer arithmetic operation ram to register transfer register to register transfer group- ing group- ing 54 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. list of instruction function (continued) function (t1f) = 1 ? after skipping (t1f) ? 0 (t2f) = 1 ? after skipping (t2f) ? 0 (t3f) = 1 ? after skipping (t3f) ? 0 (t4f) = 1 ? after skipping (t4f) ? 0 (a) ? (p0) (p0) ? (a) (a) ? (p1) (p1) ? (a) (a 2 Ca 0 ) ? (p2 2 Cp2 0 ) (a 3 ) ? 0 (d) ? 1 (d(y)) ? 0 (y) = 0 to 7 (d(y)) ? 1 (y) = 0 to 7 (d(y)) = 0 ? (y) = 0 to 7 (k0) ? (a) (a) ? (k0) (pu0) ? (a) (a) ? (pu0) mnemonic snzt1 snzt2 snzt3 snzt4 iap0 op0a iap1 op1a iap2 cld rd sd szd tk0a tak0 tpu0a tapu0 input/output operation function (a) ? (w4) (w4) ? (a) (b) ? (t1 7 Ct1 4 ) (a) ? (t1 3 Ct1 0 ) (r1 7 Cr1 4 ) ? (b) (t1 7 Ct1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) (t1 3 Ct1 0 ) ? (a) (b) ? (t2 7 Ct2 4 ) (a) ? (t2 3 Ct2 0 ) (r2 7 Cr2 4 ) ? (b) (t2 7 Ct2 4 ) ? (b) (r2 3 Cr2 0 ) ? (a) (t2 3 Ct2 0 ) ? (a) (b) ? (t3 7 Ct3 4 ) (a) ? (t3 3 Ct3 0 ) (r3 7 Cr3 4 ) ? (b) (t3 7 Ct3 4 ) ? (b) (r3 3 Cr3 0 ) ? (a) (t3 3 Ct3 0 ) ? (a) (b) ? (t4 7 Ct4 4 ) (a) ? (t4 3 Ct4 0 ) (r4 7 Cr4 4 ) ? (b) (t4 7 Ct4 4 ) ? (b) (r4 3 Cr4 0 ) ? (a) (t4 3 Ct4 0 ) ? (a) (r1 7 Cr1 4 ) ? (b) (r1 3 Cr1 0 ) ? (a) (r3 7 Cr3 4 ) ? (b) (r3 3 Cr3 0 ) ? (a) mnemonic taw4 tw4a tab1 t1ab tab2 t2ab tab3 t3ab tab4 t4ab tr1ab tr3ab function (inte) ? 0 (inte) ? 1 (exf0) = 1 ? after skipping (exf0) ? 0 (exf1) = 1 ? after skipping (exf1) ? 0 i1 2 = 1 : (int0) = h ? i1 2 = 0 : (int0) = l ? i2 2 = 1 : (int1) = h ? i2 2 = 0 : (int1) = l ? (a) ? (v1) (v1) ? (a) (a) ? (v2) (v2) ? (a) (a) ? (i1) (i1) ? (a) (a) ? (i2) (i2) ? (a) (a) ? (w1) (w1) ? (a) (a) ? (w2) (w2) ? (a) (a) ? (w3) (w3) ? (a) mnemonic di ei snz0 snz1 snzi0 snzi1 tav1 tv1a tav2 tv2a tai1 ti1a tai2 ti2a taw1 tw1a taw2 tw2a taw3 tw3a group- ing timer operation interrupt operation timer operation group- ing group- ing timer operation 55 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. list of instruction function (continued) mnemonic tabsi tsiab taj1 tj1a sst snzsi tabad tala tadab taq1 tq1a adst snzad taq2 tq2a function (a) ? (si 3 Csi 0 ) (b) ? (si 7 Csi 4 ) (si 3 Csi 0 ) ? (a) (si 7 Csi 4 ) ? (b) (a) ? (j1) (j1) ? (a) (siof) ? 0 serial i/o starting (siof) = 1 ? after skipping (siof) ? 0 (a) ? (ad 5 Cad 2 ) (b) ? (ad 9 Cad 6 ) however, in the com- parator mode, (a) ? (ad 3 Cad 0 ) (b) ? (ad 7 Cad 4 ) (a) ? (ad 1 , ad 0 , 0, 0) (ad 3 Cad 0 ) ? (a) (ad 7 Cad 4 ) ? (b) (a) ? (q1) (q1) ? (a) (adf) ? 0 a-d conversion starting (adf) = 1 ? after skipping (adf) ? 0 (a) ? (q2) (q2) ? (a) mnemonic nop pof epof snzp wrst tamr tmra function (pc) ? (pc) + 1 ram back-up pof instruction valid (p) = 1 ? (wdf1) ? 0, (wef) ? 1 (a) ? (mr) (mr) ? (a) serial i/o control operation other operation a-d conversion operation group- ing group- ing 56 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. instruction code table d 3 Cd 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 Cd 4 00 nop C pof snzp di ei rc sc C C am amc tya C tba C 000001 01 bla cld C iny rd sd C dey and or teab C cma rar tab tay 000010 02 szb 0 szb 1 szb 2 szb 3 szd sean seam C C tda tabe C C C C szc 000011 03 bmla C C C C C C C snz0 snz1 snzi0 snzi1 C C tv2a tv1a 000100 04 C C C C rt rts rti C lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 000101 05 tasp tad tax taz tav1 tav2 C C C C C epof sb 0 sb 1 sb 2 sb 3 000110 06 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 000111 07 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 001000 08 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 001001 09 tabp 16*** tabp 17*** tabp 18*** tabp 19*** tabp 20*** tabp 21*** tabp 22*** tabp 23*** tabp 24*** tabp 25*** tabp 26*** tabp 27*** tabp 28*** tabp 29*** tabp 30*** tabp 31*** 001010 0a C C C C C C C C C C C C C C C C 001011 0b C C C C C C C C C C C C C C C C 001100 0c 001101 0d 001110 0e 001111 0f bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 010000 010111 011000 011111 18C1f b b b b b b b b b b b b b b b b bl bml bla bmla sea szd the second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 ? *** cannot be used in the m34512m2-xxxfp. 10C17 000000 the above table shows the relationship between machine language codes and machine language instructions. d 3 Cd 0 show the low-order 4 bits of the machine language code, and d 9 Cd 4 show the high-order 6 bits of the machine language code. the hexadecimal representa- tion of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each i nstruction is shown. do not use code marked C. the codes for the second word of a two-word instruction are described below. 57 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. instruction code table (continued) C C tj1a C tq1a tq2a C C C C C C C C tw1a tw2a tw3a tw4a C C C C tmra ti1a ti2a C C tk0a C C C C t1ab t2ab t3ab t4ab C C C C tsiab tadab C tr3ab C C C tr1ab C C taj1 C taq1 taq2 C C C tala C taw1 taw2 taw3 taw4 C C C tamr tai1 tai2 C tak0 tapu0 C C C C C C C C iap0 iap1 iap2 C C C C C C C C C C C C C tab1 tab2 tab3 tab4 C C C C tabsi tabad C C C C C C snzt1 snzt2 snzt3 snzt4 C C C snzad snzsi C C C C C C C C C C C C C C C C C C C C C sst adst wrst C C C C C C C C C C C C C C C tam 0 tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 xam 0 xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 xami 0 xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 xamd 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy tma 0 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 bl bml bla bmla sea szd the second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 op0a op1a C C C C C C C C C C C tpu0a C C d 3 Cd 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 Cd 4 20 100001 21 100010 22 100011 23 100100 24 100101 25 100110 26 100111 27 101000 28 101001 29 101010 2a 101011 2b 101100 2c 101101 2d 101110 2e 101111 2f 110000 111111 30C3f 100000 the above table shows the relationship between machine language codes and machine language instructions. d 3 Cd 0 show the low- order 4 bits of the machine language code, and d 9 Cd 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked C. the codes for the second word of a two-word instruction are described below. parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 58 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. (a) (b) (b) (a) (a) (y) (y) (a) (e 7 Ce 4 ) (b) (e 3 Ce 0 ) (a) (b) (e 7 Ce 4 ) (a) (e 3 Ce 0 ) (dr 2 Cdr 0 ) (a 2 Ca 0 ) (a 2 Ca 0 ) (dr 2 Cdr 0 ) (a 3 ) 0 (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 (a) (x) (a 2 Ca 0 ) (sp 2 Csp 0 ) (a 3 ) 0 (x) x, x = 0 to 15 (y) y, y = 0 to 15 (z) z, z = 0 to 3 (y) (y) + 1 (y) (y) C 1 (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (a) ? (m(dp)) (x) (x)exor(j) j = 0 to 15 (a) ? (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) C 1 (a) ? (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 tab tba tay tya teab tabe tda tad taz tax tasp lxy x, y lz z iny dey tam j xam j xamd j xami j tma j machine instructions 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 00010010z 1 z 0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01e 00e 01f 00c 01a 02a 029 051 053 052 050 3xy 048 +z 013 017 2cj 2dj 2fj 2ej 2bj 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ram addresses ram to register transfer register to register transfer skip condition datailed description carry flag cy 59 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of registers a and b to register e. transfers the contents of register e to registers a and b. transfers the contents of register a to register d. transfers the contents of register d to register a. transfers the contents of register z to register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. after transferring the contents of register a to m(dp), an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. C C C C C C C C C C C continuous description C (y) = 0 (y) = 15 C C (y) = 15 (y) = 0 C C C C C C C C C C C C C C C C C C C C C parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 60 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. note : p is 0 to 15 for m34512m2, p is 0 to 31 for M34512M4. machine instructions (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 07 n 08 p +p 00 a 00 b 06 n 01 8 01 9 00 7 00 6 02 f 01 c 01 d 05 c +j 04 c +j 02 j 02 6 02 5 07 n 000111nnnn 0010p 5 p 4 p 3 p 2 p 1 p 0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn la n t abp p am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 arithmetic operation comparison operation bit operation (a) ? n n = 0 to 15 (sp) ? (sp) + 1 (sk(sp)) ? (pc) (pc h ) ? p (pc l ) ? (dr 2 edr 0 , a 3 ea 0 ) (b) ? (rom(pc)) 7 e 4 (a) ? (rom(pc)) 3 e 0 (pc) ? (sk(sp)) (sp) ? (sp) e 1 (note) (a) ? (a) + (m(dp)) (a) ? (a) + (m(dp)) + (cy) (cy) ? carry (a) ? (a) + n n = 0 to 15 (a) ? (a) and (m(dp)) (a) ? (a) or (m(dp)) (cy) ? 1 (cy) ? 0 (cy) = 0 ? (a) ? (a) ? cy ? a 3 a 2 a 1 a 0 (mj(dp)) ? 1 j = 0 to 3 (mj(dp)) ? 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? n = 0 to 15 skip condition datailed description carry flag cy 61 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. continuous description C C C overflow = 0 C C C C (cy) = 0 C C C C (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n C C C 0/1 C C C 1 0 C C 0/1 C C C C C loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad- dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, 1 stage of stack register is used. adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy re- mains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. takes the and operation between the contents of register a and the contents of m(dp), and stores the re- sult in register a. takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is 0. stores the ones complement for register as contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. skips the next instruction when the contents of register a is equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 62 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. b a bl p, a bla p bm a bml p, a bmla p rti rt rts di ei snz0 snz1 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 10p 5 p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 10p 5 p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 0000000100 0000000101 0000111000 0000111001 18a +a 0ep +p 2pa +a 010 2pp 1aa 0cp +p 2pa +a 030 2pp 046 044 045 004 005 038 039 1 2 2 1 2 2 1 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 1 1 1 1 subroutine operation return operation interrupt operation machine instructions (continued) (pc l ) a 6 Ca 0 (pc h ) p (pc l ) a 6 Ca 0 (note) (pc h ) p (pc l ) (dr 2 Cdr 0 , a 3 Ca 0 ) (note) (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 Ca 0 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 Ca 0 (note) (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 Cdr 0 ,a 3 Ca 0 ) (note) (pc) (sk(sp)) (sp) (sp) C 1 (pc) (sk(sp)) (sp) (sp) C 1 (pc) (sk(sp)) (sp) (sp) C 1 (inte) 0 (inte) 1 (exf0) = 1 ? after skipping (exf0) 0 (exf1) = 1 ? after skipping (exf1) 0 branch operation note : p is 0 to 15 for m34512m2, p is 0 to 31 for M34512M4. skip condition datailed description carry flag cy 63 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. C C C C C C C C skip at uncondition C C (exf0) = 1 (exf1) = 1 branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous de- scription of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. clears (0) to the interrupt enable flag inte, and disables the interrupt. sets (1) to the interrupt enable flag inte, and enables the interrupt. skips the next instruction when the contents of exf0 flag is 1. after skipping, clears (0) to the exf0 flag. skips the next instruction when the contents of exf1 flag is 1. after skipping, clears (0) to the exf1 flag. C C C C C C C C C C C C C parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 64 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. machine instructions (continued) snzi0 snzi1 tav1 tv1a tav2 tv2a tai1 ti1a tai2 ti2a taw1 tw1a taw2 tw2a taw3 tw3a taw4 tw4a tab1 t1ab tab2 t2ab i1 2 = 1 : (int0) = h ? i1 2 = 0 : (int0) = l ? i2 2 = 1 : (int1) = h ? i2 2 = 0 : (int1) = l ? (a) (v1) (v1) (a) (a) (v2) (v2) (a) (a) (i1) (i1) (a) (a) (i2) (i2) (a) (a) (w1) (w1) (a) (a) (w2) (w2) (a) (a) (w3) (w3) (a) (a) (w4) (w4) (a) (b) (t1 7 Ct1 4 ) (a) (t1 3 Ct1 0 ) (r1 7 Cr1 4 ) (b) (t1 7 Ct1 4 ) (b) (r1 3 Cr1 0 ) (a) (t1 3 Ct1 0 ) (a) (b) (t2 7 Ct2 4 ) (a) (t2 3 Ct2 0 ) (r2 7 Cr2 4 ) (b) (t2 7 Ct2 4 ) (b) (r2 3 Cr2 0 ) (a) (t2 3 Ct2 0 ) (a) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 03a 03b 054 03f 055 03e 253 217 254 218 24b 20e 24c 20f 24d 210 24e 211 270 230 271 231 0000111010 0000111011 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001010100 1000011000 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 1001001110 1000010001 1001110000 1000110000 1001110001 1000110001 interrupt operation timer operation skip condition datailed description carry flag cy 65 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. when bit 2 (i1 2 ) of register i1 is 1 : skips the next instruction when the level of int0 pin is h. when bit 2 (i1 2 ) of register i1 is 0 : skips the next instruction when the level of int0 pin is l. when bit 2 (i2 2 ) of register i2 is 1 : skips the next instruction when the level of int1 pin is h. when bit 2 (i2 2 ) of register i2 is 0 : skips the next instruction when the level of int1 pin is l. transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register v2 to register a. transfers the contents of register a to interrupt control register v2. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. transfers the contents of interrupt control register i2 to register a. transfers the contents of register a to interrupt control register i2. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w3 to register a. transfers the contents of register a to timer control register w3. transfers the contents of timer control register w4 to register a. transfers the contents of register a to timer control register w4. transfers the contents of timer 1 to registers a and b. transfers the contents of registers a and b to timer 1 and timer 1 reload register. transfers the contents of timer 2 to registers a and b. transfers the contents of registers a and b to timer 2 and timer 2 reload register. C C C C C C C C C C C C C C C C C C C C C C C C (int0) = h however, i1 2 = 1 (int0) = l however, i1 2 = 0 (int1) = h however, i2 2 = 1 (int1) = l however, i2 2 = 0 C C C C C C C C C C C C C C C C C C C C parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 66 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. machine instructions (continued) tab3 t3ab tab4 t4ab tr1ab tr3ab snzt1 snzt2 snzt3 snzt4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 272 232 273 233 23f 23b 280 281 282 283 1001110010 1000110010 1001110011 1000110011 1000111111 1000111011 1010000000 1010000001 1010000010 1010000011 (b) (t3 7 Ct3 4 ) (a) (t3 3 Ct3 0 ) (r3 7 Cr3 4 ) (b) (t3 7 Ct3 4 ) (b) (r3 3 Cr3 0 ) (a) (t3 3 Ct3 0 ) (a) (b) (t4 7 Ct4 4 ) (a) (t4 3 Ct4 0 ) (r4 7 Cr4 4 ) (b) (t4 7 Ct4 4 ) (b) (r4 3 Cr4 0 ) (a) (t4 3 Ct4 0 ) (a) (r1 7 Cr1 4 ) (b) (r1 3 Cr1 0 ) (a) (r3 7 Cr3 4 ) (b) (r3 3 Cr3 0 ) (a) (t1f) = 1 ? after skipping (t1f) 0 (t2f) = 1 ? after skipping (t2f) 0 (t3f) = 1 ? after skipping (t3f) 0 (t4f) = 1 ? after skipping (t4f) 0 timer operation skip condition datailed description carry flag cy 67 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. C C C C C C C C C C C C C C C C (t1f) = 1 (t2f) =1 (t3f) = 1 (t4f) = 1 transfers the contents of timer 3 to registers a and b. transfers the contents of registers a and b to timer 3 and timer 3 reload register. transfers the contents of timer 4 to registers a and b. transfers the contents of registers a and b to timer 4 and timer 4 reload register. transfers the contents of registers a and b to timer 1 reload register. transfers the contents of registers a and b to timer 3 reload register. skips the next instruction when the contents of t1f flag is 1. after skipping, clears (0) to t1f flag. skips the next instruction when the contents of t2f flag is 1. after skipping, clears (0) to t2f flag. skips the next instruction when the contents of t3f flag is 1. after skipping, clears (0) to t3f flag. skips the next instruction when the contents of t4f flag is 1. after skipping, clears (0) to t4f flag. parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 68 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. machine instructions (continued) iap0 op0a iap1 op1a iap2 cld rd sd szd tk0a tak0 tpu0a tapu0 tabsi tsiab taj1 tj1a sst snzsi 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 260 220 261 221 262 011 014 015 024 02b 21b 256 22d 257 278 238 242 202 29e 288 1001100000 1000100000 1001100001 1000100001 1001100010 0000010001 0000010100 0000010101 0000100100 0000101011 1000011011 1001010110 1000101101 1001010111 1001111000 1000111000 1001000010 1000000010 1010011110 1010001000 input/output operation (a) (p0) (p0) (a) (a) (p1) (p1) (a) (a 2 Ca 0 ) (p2 2 Cp2 0 ) (a 3 ) 0 (d) 1 (d(y)) 0 (y) = 0 to 7 (d(y)) 1 (y) = 0 to 7 (d(y)) = 0 ? (y) = 0 to 7 (k0) (a) (a) (k0) (pu0) (a) (a) (pu0) (a) (si 3 Csi 0 ) (b) (si 7 Csi 4 ) (si 3 Csi 0 ) (a) (si 7 Csi 4 ) (b) (a) (j1) (j1) (a) (siof) 0 serial i/o starting (siof) = 1 ? after skipping (siof) 0 serial i/o control operation skip condition datailed description carry flag cy 69 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. C C C C C C C C C C C C C C C C C C C C C C C C C C C (d(y)) = 0 (y) = 0 to 7 C C C C C C C C C (siof) = 1 transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to register a. sets (1) to port d. clears (0) to a bit of port d specified by register y. sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is 0. transfers the contents of register a to key-on wakeup control register k0. transfers the contents of key-on wakeup control register k0 to register a. transfers the contents of register a to pull-up control register pu0. transfers the contents of pull-up control register pu0 to register a. transfers the contents of serial i/o register si to registers a and b. transfers the contents of registers a and b to serial i/o register si. transfers the contents of serial i/o mode register j1 to register a. transfers the contents of register a to serial i/o mode register j1. clears (0) to siof flag and starts serial i/o. skips the next instruction when the contents of siof flag is 1. after skipping, clears (0) to siof flag. parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation 70 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. machine instructions (continued) tabad tala tadab taq1 tq1a adst snzad taq2 tq2a nop pof epof snzp wrst tamr tmra 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 279 249 239 244 204 29f 287 245 205 000 002 05b 003 2a0 252 216 1001111001 1001001001 1000111001 1001000100 1000000100 1010011111 1010000111 1001000101 1000000101 0000000000 0000000010 0001011011 0000000011 1010100000 1001010010 1000010110 a-d conversion operation other operation (a) (ad 5 Cad 2 ) (b) (ad 9 Cad 6 ) however, in the comparator mode, (a) (ad 3 Cad 0 ) (b) (ad 7 Cad 4 ) (a) (ad 1 , ad 0 , 0, 0) (ad 3 Cad 0 ) (a) (ad 7 Cad 4 ) (b) (a) (q1) (q1) (a) (adf) 0 a-d conversion starting (adf) = 1 ? after skipping (adf) 0 (a) (q2) (q2) (a) (pc) (pc) + 1 ram back-up pof instruction valid (p) = 1 ? (wdf1) 0 (wef) 1 (a) (mr) (mr) (a) skip condition datailed description carry flag cy 71 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. C C C C C C (adf) = 1 C C C C C (p) = 1 C C C C C C C C C C C C C C C C C C C transfers the high-order 8 bits of the contents of register ad to registers a and b. transfers the low-order 2 bits of the contents of register ad to the high-order 2 bits of the contents of regis- ter a. simultaneously, the low-order 2 bits of the contents of the register a is 0. transfers the contents of registers a and b to the comparator register at the comparator mode. transfers the contents of the a-d control register q1 to register a. transfers the contents of register a to the a-d control register q1. clears the adf flag, and the a-d conversion at the a-d conversion mode or the comparator operation at the comparator mode is started. skips the next instruction when the contents of adf flag is 1. after skipping, clears (0) the contents of adf flag. transfers the contents of the a-d control register q2 to register a. transfers the contents of register a to the a-d control register q2. no operation puts the system in ram back-up state by executing the pof instruction after executing the epof instruction. makes the immediate pof instruction valid by executing the epof instruction. skips the next instruction when p flag is 1. after skipping, p flag remains unchanged. operates the watchdog timer and initializes the watchdog timer flag wdf1. transfers the contents of the clock control register mr to register a. transfers the contents of register a to the clock control register mr. 72 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. parameter supply voltage input voltage p0, p1, p2, int0, int1, reset , x in input voltage d 0 Cd 7 input voltage a in0 Ca in3 output voltage p0, p1, reset output voltage d 0 Cd 7 output voltage x out power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state ta = 25 c symbol v dd v i v i v i v o v o v o p d topr tstg unit v v v v v v v mw c c ratings C0.3 to 7.0 C0.3 to v dd +0.3 C0.3 to 13 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to 13 C0.3 to v dd +0.3 300 C20 to 85 C40 to 125 absolute maximum raings symbol v dd v ram v ss v ih v ih v ih v ih v il v il v il i ol (peak) i ol (peak) i ol (peak) i ol (peak) i ol (avg) i ol (avg) i ol (avg) i ol (avg) s i ol (avg) f(x in ) tw(s ck ) parameter supply voltage ram back-up voltage (at ram back-up mode) supply voltage h level input voltage p0, p1, p2, x in h level input voltage d 0 Cd 7 h level input voltage reset h level input voltage s in , s ck , int0, int1 l level input voltage p0, p1, p2, d 0 Cd 7 , x in l level input voltage reset l level input voltage s in , s ck , int0, int1 l level peak output current reset l level peak output current d 6 , d 7 l level peak output current d 0 Cd 5 l level peak output current p0, p1, s ck , s out l level average output current reset (note) l level average output current d 6 , d 7 (note) l level average output current d 0 Cd 5 (note) l level average output current p0, p1, s ck , s out (note) l level total average current d, reset , s ck , s out l level total average current p0, p1 oscillation frequency (at ceramic resonance) oscillation frequency (at external clock input) serial i/o external clock cycle (pulse width of h and l) note: the average output current (i ol ) is the average value during 100 ms. unit v ma mhz ns conditions f(x in ) 4.2 mhz v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 5.0 v v dd = 4.0 v to 5.5 v v dd = 4.0 v to 5.5 v v dd = 4.0 v to 5.5 v max. 5.5 v dd 12 v dd v dd 0.2v dd 0.3v dd 0.15v dd 10 40 24 24 5 30 15 12 80 80 4.2 3.0 limits min. 4.0 1.8 0.8v dd 0.8v dd 0.85v dd 0.85v dd 0 0 0 750 typ. 0 recommended operating conditions (ta = C20 c to 85 c, v dd = 4.0 v to 5.5 v, unless otherwise noted) 73 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. electrical characteristics (ta = C20 c to 85 c, v dd = 4.0 v to 5.5 v, unless otherwise noted) symbol v ol v ol v ol v ol i ih i ih i il i il i dd r pu v t+ C v tC v t+ C v tC parameter l level output voltage p0, p1 l level output voltage reset l level output voltage d 6 , d 7 l level output voltage d 0 Cd 5 h level input current p0, p1, p2, reset h level input current d 0 Cd 7 l level input current p0, p1, p2, reset l level input current d 0 Cd 7 supply current pull-up resistor value hysteresis int0, int1, s in , s ck hysteresis reset at active mode at ram back-up mode unit v v v v m a m a m a m a ma m a k w v v test conditions v dd = 5 v v dd = 5 v v dd = 5 v v dd = 5 v v i = v dd v i = 12 v v i = 0 v no pull-up of ports p0 and p1 v i = 0 v v dd = 5 v middle-speed mode v dd = 5 v high-speed mode ta = 25 c v dd = 5 v v dd = 5 v v dd = 5 v v dd = 5 v limits max. 2 2 2 0.9 2 1 1 5.5 1.5 9.0 1.8 1 10 125 i ol = 12 ma i ol = 5 ma i ol = 30 ma i ol = 10 ma i ol = 15 ma f(x in ) = 4.0 mhz f(x in ) = 400 khz f(x in ) = 4.0 mhz f(x in ) = 400 khz v i = 0 v min. C1 C1 20 typ. 1.8 0.5 3.0 0.6 0.1 50 0.3 1.5 basic timing diagram x in (system clock = f(x in )) mi mi+1 x in (system clock = f(x in )/2) int0,int1 clock port d output port d input port p0, p1 output port p0, p1, p2 input interrupt input machine cycle pin name parameter p0 0 ?0 3 p1 0 ?1 3 p0 0 ?0 3 p1 0 ?1 3 p2 0 ?2 2 d 0 ? 7 d 0 ? 7 74 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. a-d converter recommended operating conditions (comparator mode included, ta = C20 c to 85 c, unless otherwise noted) symbol v dd v ia f(x in ) parameter supply voltage analog input voltage oscillation frequency a-d converter characteristics (ta = C20 c to 85 c, unless otherwise noted) conditions unit v v mhz mhz middle-speed mode high-speed mode min. 4.0 0 0.8 0.4 typ. max. 5.5 v dd limits symbol C C C v 0t v fst ia dd t conv C C C parameter resolution linearity error differential non-linearity error zero transition voltage full-scale transition voltage aCd operating current a-d conversion time comparator resolution comparator error (note) comparator comparison time test conditions unit bits lsb lsb mv mv ma m s bits mv m s ta = C25 c to 85 c, v dd = 4.0 v to 5.5 v ta = C25 c to 85 c, v dd = 4.0 v to 5.5 v v dd = 5.12 v v dd = 5.12 v v dd = 5.0 v f(x in ) = 0.4 mhz to 4.0 mhz f(x in ) = 4.0 mhz, middle-speed mode f(x in ) = 4.0 mhz, high-speed mode comparator mode v dd = 5.12 v f(x in ) = 4.0 mhz, middle-speed mode f(x in ) = 4.0 mhz, high-speed mode min. 0 5105 typ. 5 5115 0.7 max. 10 2 0.9 20 5125 2.0 93.0 46.5 8 20 12 6 limits note: as for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logi c value of the comparison volt- age v ref which is generated by the built-in da converter can be obtained by the following formula. logic value of comparison voltage v ref v ref = 5 n n = value of register ad (n = 0 to 255) v dd 256 75 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] 1. confirmation specify the type of eproms submitted. three sets of eproms are required for each pattern (check in the approximate box). if at least two of the three sets of eproms submitted contai n the identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differ from this data. thus, the customer must be especially careful in verifying the data contained in the eproms submitted. checksum code for entire eprom area (hexadecimal notation) eprom type: company name date issued date: ] customer 27c256 27c512 low-order 5-bit data high-order 5-bit data 0000 16 07ff 16 4000 16 47ff 16 7fff 16 2.00k 2.00 k low-order 5-bit data high-order 5-bit data 0000 16 07ff 16 4000 16 47ff 16 ffff 16 2.00k 2.00k set ff 16 in the shaded area. set 111 2 in the area of low-order and high-order 5-bit dat a. ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the approximate mark specification form (32p6b-a fo r m34512m2-xxxfp) and attach to the mask rom order confirmation form. ] 3. comments t e l ( ) mask rom number date: section head signature supervisor signature responsible officer supervisor issuance s ignature receipt gzz-sh52-47b <81a0> 4500 series mask rom order confirmation form single-chip microcomputer m34512m2-xxxfp mitsubishi electric please fill in all items marked ] . 76 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminar y notice: this is not a final specification. some parametric limits are subject to change. ] specify the type of eproms submitted. three sets of eproms are required for each pattern (check in the approximate box). if at least two of the three sets of eproms submitted contai n the identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differ from this data. thus, the customer must be especially careful in verifying the data contained in the eproms submitted. checksum code for entire eprom area (hexadecimal notation) eprom type: company name date issued date: ] customer 27c256 27c512 low-order 5-bit data high-order 5-bit data 0000 16 0fff 16 4000 16 4fff 16 7fff 16 4.00k 4.00 k low-order 5-bit data high-order 5-bit data 0000 16 0fff 16 4000 16 4fff 16 ffff 16 4.00k 4.00k set ff 16 in the shaded area. set 111 2 in the area of low-order and high-order 5-bit dat a. ] 2. mark specification mark specification must be submitted using the correct form for the type of package being ordered. fill out the approximate mark specification form (32p6b-a fo r M34512M4-xxxfp) and attach to the mask rom order confirmation form. ] 3. comments t e l ( ) mask rom number date: section head signature supervisor signature responsible officer supervisor issuance s ignature receipt gzz-sh52-46b <81a0> 4500 series mask rom order confirmation form single-chip microcomputer M34512M4-xxxfp mitsubishi electric please fill in all items marked ] . 1. confirmation 77 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. 32p6b (32-pin lqfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b), and enter the mitsubishi catalog name and the special mark (if needed). a. standard mitsubishi mark b. customers parts number + mitsubishi catalog name mitsubishi ic catalog name mitsubishi ic catalog name note: if the mitsubishi logo is not required, check the box on the right. customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. (the mitsubishi logo is not marked.) 3 : customers parts number can be up to 7 characters : only 0 ~ 9, a ~ z, (hyphen), . (periods), , (commas) are usable. 1 32 8 9 16 25 17 24 mitsubishi lot number (4-digit or 5-digit) 1 32 8 9 16 25 17 24 mitsubishi logo is not required c. customers parts number customers parts number note : the fonts and size of characters are standard mitsubishi type. shaded area: mitsubishi lot number (4-digit or 5-digit) and mask rom number (3-digit) are always marked, for products classi- fication. note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 11 characters : only 0 ~ 9, a ~ z, (hyphen), . (periods), , (commas) are usable. 1 32 8 9 16 25 17 24 78 4512 group single-chip 4-bit cmos microcomputer mitsubishi microcomputers preliminary notice: this is not a final specification. some parametric limits are subject to change. lqfp32-p-77-0.80 weight(g) jedec code eiaj package code lead material alloy 42 32p6b-a plastic 32pin 7 5 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.5 i 2 1.0 m d 7.4 m e 7.4 10 0 0.1 1.0 0.7 0.5 0.3 9.2 9.0 8.8 9.2 9.0 8.8 0.8 7.1 7.0 6.9 7.1 7.0 6.9 0.175 0.125 0.105 0.45 0.35 0.3 1.4 0 1.7 e e e e c h e 1 8 9 32 25 24 16 17 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f package outline ? 1998 mitsubishi electric corp. new publication, effective dec. 1998. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. rev. rev. no. date 1.0 first edition 981218 revision description list 4512 group data sheet (1/1) revision description |
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